IP Library Granted Patent US 8,525,176
Granted Patent B2
US 8,525,176 · App. 13/186,564 · Granted Sep 3, 2013

Thin film transistor, display device using the same, and thin film transistor manufacturing method

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Quick Facts
Patent No.
US 8,525,176
App. No.
13/186,564
Granted
Sep 3, 2013
Kind
B2
Abstract

A TFT includes a supporting substrate, a gate electrode formed on the supporting substrate, a gate insulation film formed on the substrate so as to cover the gate electrode, a first semiconductor layer formed across from the gate electrode with respect to the gate insulation film, a second semiconductor layer formed on the first semiconductor layer, and having a first thickness and a second thickness which is greater than the first thickness, an ohmic contact layer formed on the second semiconductor layer, and a source electrode and a drain electrode formed on the ohmic contact layer, spacing apart with each other.

Claims (47)

1. A thin-film transistor (TFT) comprising:

a substrate;

a gate electrodes disposed above said substrate;

a gate insulation film disposed on said substrate so as to cover said gate electrode;

a first semiconductor layer disposed across from said gate electrode with respect to said gate insulation film;

a second semiconductor layer disposed on said first semiconductor layer, and having a first portion with a first thickness and a second portion with a second thickness, the second thickness being greater than the first thickness;

an ohmic contact layer disposed on said second semiconductor layer; and

a source electrode and a drain electrode disposed on said ohmic contact layer, said source electrode and said drain electrode being spaced apart from each other.

2. The TFT according to claim 1 ,

wherein the second portion is a center portion of the second semiconductor layer, and

the first portion is an end portion of said second semiconductor layer.

3. The TFT according to claim 1 ,

wherein a difference between the first thickness and the second thickness is from 50 nm to 300 nm inclusive.

4. The TFT according to claim 1 ,

wherein said second semiconductor layer is formed in a projected shape having the first portion and the second portion.

5. The TFT according to claim 1 , further comprising

a separating part separating said source electrode and said drain electrode from each other,

wherein said second semiconductor layer has a part of said separating part formed in a center portion of said second semiconductor layer.

6. The TFT according to claim 1 ,

wherein said second semiconductor layer is a buffer layer.

7. The TFT according to claim 1 ,

wherein said second semiconductor layer is an amorphous silicon film.

8. The TFT according to claim 1 ,

wherein said second semiconductor layer and said ohmic contact layer share an interface with each other, and said second semiconductor layer and said first semiconductor layer share an interface with each other.

9. The TFT according to claim 1 ,

wherein said second semiconductor layer has a lower mobility of carriers than said first semiconductor.

10. The TFT according to claim 1 ,

wherein said ohmic contact layer coats sides of both end portions of said first semiconductor layer and said second semiconductor layer in a channel length direction.

11. The TFT according to claim 1 ,

wherein, in a cross section of said TFT perpendicular to said substrate, said gate electrode is longer than a width of said separating part between said source electrode and said drain electrode.

12. The TFT according to claim 11 ,

wherein said first semiconductor layer is longer than said gate electrode.

13. The TFT according to claim 1 ,

wherein, in a cross section of said TFT perpendicular to said substrate, a width of said separating part between said source electrode and said drain electrode is longer than said gate electrode.

14. A display apparatus comprising said TFT according to claim 1 .

15. A method for manufacturing a TFT, said method comprising:

forming a gate electrode above a substrate;

forming a gate insulation film on the substrate so as to cover the gate electrode;

forming a first semiconductor layer across from the gate electrode with respect to the gate insulation film;

forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a first portion with a first thickness and a second portion with a second thickness, the second thickness being greater than the first thickness;

forming an ohmic contact layer on the second semiconductor layer; and

forming, on the ohmic contact layer, a source electrode and a drain electrode being spaced apart from each other.

16. The method for manufacturing the TFT according to claim 15 ,

wherein said forming the second semiconductor includes

forming of the second semiconductor layer having the second portion,

applying a photoresist mask to a part of the second semiconductor layer, and

etching the second semiconductor layer so as to form the second semiconductor layer having the first portion and the second portion.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2015
From: PANASONIC CORPORATION
To: JOLED INC
Reel/Frame 035187/0483 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2011
From: SATOH, EIICHI
To: PANASONIC CORPORATION
Reel/Frame 026977/0901 →