M-pair mode protection switching
View Patent ↗A communication comprises a plurality of digital subscriber line (DSL) links, a first node having at least one application port configured for an elastic service and a plurality of DSL ports, and a second node having at least one application port configured for an elastic service and a plurality of DSL ports. Each of the first and second nodes is configured to interleave data received over the at least one application port across the plurality of DSL ports, each DSL port allocated a set of DSL timeslots for transport of the data received over the at least one application port. When a failure is detected on one of the DSL links, each of the first and second nodes is configured to interleave the data received over the at least one application port across the remaining DSL ports not connected to the failed DSL link without adjusting the set of DSL timeslots allocated to each of the remaining DSL ports for transport of the data from the at least one application port.
1. A communication unit comprising:
at least one application port configured for an elastic service;
a plurality of digital subscriber line (DSL) transceivers each coupled to a respective DSL link; and
a processing circuit coupled to the at least one application port and the plurality of DSL transceivers, the processing circuit configured to provide a copy of data received from the at least one application port to each of the plurality of DSL transceivers via a respective data stream comprising timeslots, the processing circuit further configured to provide a timeslot map to each of the DSL transceivers, the timeslot map indicating which of the timeslots in the data stream are to be processed by each respective DSL transceiver such that the data from the at least one application port is interleaved across the plurality of DSL transceivers;
wherein when a failure is detected on one of the DSL links, the processing circuit is configured to update the timeslot map such that the data from the at least one application port is interleaved across the remaining DSL transceivers not connected to the failed DSL link without changing the respective number of timeslots allocated to each remaining DSL transceiver.
2. The communication unit of claim 1 , wherein the processing circuit is a field programmable gate array (FPGA).
3. The communication unit of claim 1 , wherein the elastic service is an Ethernet service; and
wherein the communication unit further comprises one or more high-level data link (HDLC) encoders configured to HDLC encode an Ethernet signal received over the at least one application port.
4. The communication unit of claim 3 , wherein the at least one application port is configured to use an Ethernet flow control protocol to delay data received at the at least one application port while the timeslot map is updated.
5. The communication unit of claim 1 , wherein the processing circuit is configured to update the timeslot map to include the DSL transceiver coupled to the failed DSL link when the failed DSL link recovers.
6. The communication unit of claim 1 , wherein each of the DSL transceivers is configured according to the G.SHDSL standard.
7. The communication unit of claim 1 , wherein the at least one application port comprises a plurality of application ports, each of the plurality of application ports configured for an elastic service.
8. The communication unit of claim 1 , wherein the processing circuit is configured to provide a timeslot map such that the data from the at least one application port is interleaved across the plurality of DSL transceivers circularly and serially.