Fabricating and operating a memory array having a multi-level cell region and a single-level cell region
View Patent ↗Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.
1. A method of forming a memory array of non-volatile storage elements, the method comprising:
forming a first region including a first plurality of floating gate stacks above a substrate, the first region is for multi-level non-volatile storage elements;
forming a second region including a second plurality of floating gate stacks above the substrate, the second region is for single-level non-volatile storage elements;
implanting ions having a first concentration in the substrate for source/drain regions in the first region;
implanting ions having a second concentration in the substrate near the source/drain regions in the first region, the conductivity type of the first concentration of ions is opposite the conductivity type of the second concentration of ions;
implanting a third concentration of ions in the substrate for source/drain regions in the second region; and
implanting a fourth concentration of zero or more ions in the substrate near the source/drain regions in the second region, either the first concentration is less than the third concentration or the second concentration is greater than the fourth concentration.
2. The method of claim 1 , wherein the implanting a fourth concentration of zero or more ions includes implanting a non-zero concentration of ions as a halo implant, the second concentration is a halo implant, the first concentration and the second concentration are a first ratio, the third concentration and the fourth concentration are a second ratio, the second ratio is higher than the first ratio.
3. The method of claim 1 , wherein the implanting ions having a first concentration for source/drain regions in the first region and the implanting a third concentration of ions for source/drain regions in the second region includes:
implanting ions of a first conductivity type in the first region and the second region;
masking the first region; and
implanting ions of the first conductivity type in the second region, the first concentration is less than the third concentration.
4. The method of claim 1 , wherein the implanting ions having a second concentration in the first region and the implanting ions having a fourth concentration in the second region includes:
implanting ions of a first conductivity type in the first region and the second region;
masking the second region; and
implanting ions of the first conductivity type in the first region, the second concentration is greater than the fourth concentration.
5. The method of claim 1 , wherein the forming a first region including a first plurality of floating gate stacks and the forming a second region including a second plurality of floating gate stacks includes:
forming a first region including a first plurality of polysilicon strips to be used to form first floating gates above the substrate;
forming a second region including a second plurality of polysilicon strips to be used to form second floating gates above the substrate;
depositing isolation material between adjacent ones of the first plurality of polysilicon strips and between adjacent ones of the second plurality of polysilicon strips;
performing a shallow etch back of the isolation material in the second region;
performing a deep etch back of the isolation material in the first region;
forming an inter-poly dielectric layer above the first floating gates in the first region and above the second floating gates in the second region; and
forming first control gates above the first floating gates in the first region and second control gates above the second floating gates in the second region.
6. The method of claim 5 , wherein:
the performing a deep etch back includes etching back the isolation material to a first level to achieve a first coupling ratio between the first floating gates and the first control gates; and
the performing a shallow etch back of the material in the second region includes etching back the isolation material to a first level to achieve a second coupling ratio between the second floating gates and the second control gates, the second coupling ratio is lower than the first coupling ratio.
7. The method of claim 1 , wherein the forming the first region includes forming the multi-level non-volatile storage elements arraigned as a first plurality of NAND strings, the forming the second region includes forming the single-level non-volatile storage elements arraigned as a second plurality of NAND strings.
8. The method of claim 7 , further comprising:
forming first shallow trench isolation structures that separate adjacent ones of the first plurality of NAND strings; and
forming second shallow trench isolation structures that separate adjacent ones of the second plurality of NAND strings, the first shallow trench isolation structures have a deep etch back and the second shallow trench isolation structures have a shallow etch back.
9. The method of claim 8 , wherein:
forming the non-volatile storage elements in the first NAND strings includes forming first floating gates and first control gates and forming the non-volatile storage elements in the second NAND strings includes forming second floating gates and second control gates;
forming the deep etch back includes forming the deep etch back at a level to achieve a first coupling ratio between the first floating gates and the first control gates; and
forming the shallow etch back includes forming the shallow etch back at a level to achieve a second coupling ratio between the second floating gates and the second control gates, the second coupling ratio is lower than the first coupling ratio.
10. The method of claim 8 , wherein:
forming the shallow etch back includes forming the shallow etch back at a level to inhibit charge from becoming trapped in the second shallow trench isolation structures when programming the second plurality of non-volatile storage elements.
11. A method of forming a memory array of non-volatile storage elements, the method comprising:
forming a first region including a first plurality of polysilicon strips to be used to form first floating gates above a substrate, the first region is for multi-level non-volatile storage elements;
forming a second region including a second plurality of polysilicon strips to be used to form second floating gates above the substrate, the second region is for single-level non-volatile storage elements;
depositing isolation material between adjacent ones of the first plurality of polysilicon strips and between adjacent ones of the second plurality of polysilicon strips;
performing a shallow etch back of the isolation material in the second region; and
performing a deep etch back of the isolation material in the first region.
12. The method of claim 11 , further comprising:
forming an inter-poly dielectric layer above the floating gates in the first region and in the second region; and
forming first control gates above the first floating gates in the first region, the performing a deep etch back includes etching to a first level to achieve a first coupling ratio between the first floating gates and the first control gates; and
forming second control gates above the second floating gates in the second region, the performing a shallow etch back includes etching to a second level to achieve a second coupling ratio between the second floating gates and the second control gates, the second coupling ratio is less than the first coupling ratio.
13. The method of claim 12 , wherein the performing a shallow etch back includes etching to the second level to prevent charge from being stored in the isolation material in the second region when programming the single-level non-volatile storage elements in the second region.
14. A method for forming a non-volatile storage system, comprising:
forming a first plurality of NAND strings of non-volatile storage elements in a first region of a memory array, the first region is for multi-level non-volatile storage elements;
forming a second plurality of NAND strings of non-volatile storage elements in a second region of the memory array, the second region is for single-level non-volatile storage elements;
forming first shallow trench isolation structures that separate adjacent ones of the first plurality of NAND strings; and
forming second shallow trench isolation structures that separate adjacent ones of the second plurality of NAND strings, the first shallow trench isolation structures have a deep etch back and the second shallow trench isolation structures have a shallow etch back.
15. The method for forming a non-volatile storage system as recited in claim 14 , further comprising:
providing one or more managing circuits in communication with the first plurality of NAND strings and the second plurality of NAND strings, the one or more managing circuits stores multiple bits per storage element in the first plurality of NAND strings and stores a single per storage element in the second plurality of NAND strings.
16. The method for forming a non-volatile storage system of claim 14 , wherein:
forming the non-volatile storage elements in the first NAND strings includes forming first floating gates and first control gates and forming the non-volatile storage elements in the second NAND strings includes forming second floating gates and second control gates;
forming the deep etch back includes forming the deep etch back at a level to achieve a first coupling ratio between the first floating gates and the first control gates; and
forming the shallow etch back includes forming the shallow etch back at a level to achieve a second coupling ratio between the second floating gates and the second control gates, the second coupling ratio is lower than the first coupling ratio.
17. The method for forming a non-volatile storage system 14 , wherein:
forming the shallow etch back includes forming the shallow etch back at a level to prevent charge from becoming trapped in the second shallow trench isolation structures when programming the non-volatile storage elements in the second NAND strings.