AT speed TAP with dual port router and command circuit
A 1149.1 TAP performs at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. In a second embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal. In a third embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states. In a fourth embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. The improvements are achieved without requiring any additional IC pins beyond the 4 required TAP pins. Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.
1. An integrated circuit comprising:
A. a TDI input lead, a TCK input lead, a TMS input lead, and a TDO output lead;
B. a test access port state machine having an input coupled to the TCK input lead, an input coupled to the TMS input lead, instruction register control outputs, a multiplexer control output, and data register control outputs;
C. an instruction register having an input coupled to the TDI input lead, inputs coupled to the instruction register control outputs, and a data register enable output;
D. a data register having an input coupled to the TDI input lead, data register control inputs, and an output;
E. a command circuit having an input coupled to the TCK input lead, an input coupled to the TMS input lead, an input coupled to the data register enable output, and data register control outputs;
F. a dual port router having inputs coupled to the data register control outputs of the state machine, inputs coupled to the data register control outputs of the command circuit, a control input coupled to the data register enable output of the instruction register, and data register control outputs coupled to the data register control inputs of the data register; and
G. multiplexer circuitry having an input coupled to the output of the instruction register, an input coupled to the output of the data register, a control input coupled to the multiplexer control output, and an output coupled to the TDO output lead.
2. The integrated circuit of claim 1 in which the state machine has states of Test Logic Reset, Run Test/Idle, SelectDR, and SelectIR.
3. The integrated circuit of claim 1 including plural data registers.