Scan driver, light emitting driver, and driving method thereof
View Patent ↗A scan driver includes: a plurality of scan driving blocks including an output terminal outputting a scan signal to a scan line; a first transistor transmitting a voltage of a power source to the output terminal; a second transistor transmitting a clock signal to the output terminal; and a third transistor including a gate electrode connected to a node formed with a gate-on voltage turning on the second transistor, one terminal connected to the power source, and the other terminal connected to the gate electrode of the first transistor. The scan driver may reduce the influence of a leakage current even though application of the scan signal is increased, and a scan signal of a uniform voltage level may be output.
1. A scan driver comprising a plurality of scan driving blocks, each of the scan driving blocks including:
an output terminal outputting a scan signal to a scan line;
a first transistor transmitting a voltage of a power source to the output terminal;
a second transistor transmitting a clock signal to the output terminal; and
a third transistor, the third transistor and the second transistor each including a gate electrode directly connected in common to a node formed with a gate-on voltage turning on the second transistor, the third transistor further including one terminal connected to the power source, and another terminal connected to a gate electrode of the first transistor,
wherein the plurality of scan driving blocks are sequentially arranged, and the node is connected to a sequence input terminal applied with the output signal of the previous arranged scan driving block or a scan start signal, and
wherein the second transistor includes:
the gate electrode connected to the node;
one terminal connected to the input terminal for the clock signal; and
another terminal connected to the output terminal.
2. The scan driver of claim 1 , wherein, when the second transistor is turned on such that the clock signal is transmitted to the output terminal, the third transistor is turned on such that the power source voltage is transmitted to the gate electrode of the first transistor to turn off the first transistor.
3. The scan driver of claim 2 , wherein the power source is a power source of a logic high level, and the first transistor is a p-channel field effect transistor.
4. The scan driver of claim 3 , wherein the second transistor and the third transistor are p-channel field effect transistors.
5. The scan driver of claim 3 , wherein the clock signal is transmitted to the output terminal as a voltage of a logic low level.
6. The scan driver of claim 1 further comprising a capacitor including one terminal connected to the node and another terminal connected to the another terminal of the second transistor.
7. The scan driver of claim 6 , wherein the capacitor is charged by the output signal of the previous arranged scan driving block or the scan start signal, and the second transistor and the third transistor are turned on by a voltage charged to the capacitor.
8. A light emitting driver, comprising:
a first input block outputting a first sequence signal;
a second input block outputting a second sequence signal; and
an output block receiving the first sequence signal and the second sequence signal to output a light emitting signal;
wherein at least one of the first input block and the second input block includes:
an output terminal transmitting one of the first sequence signal and the second sequence signal to the output block;
a first transistor transmitting a voltage of a power source to the output terminal;
a second transistor transmitting a clock signal to the output terminal; and
a third transistor, the third transistor and the second transistor each including a gate electrode directly connected in common to a first node formed with a gate-on voltage turning on the second transistor, the third transistor further including one terminal connected to the power source, and another terminal connected to a gate electrode of the first transistor.
9. The light emitting driver of claim 8 , wherein, when the second transistor is turned on such that the clock signal is transmitted to the output terminal, the third transistor is turned on such that the power source voltage is transmitted to the gate electrode of the first transistor to turn off the first transistor.
10. The light emitting driver of claim 9 , wherein the power source is a power source of a logic high level, and the first transistor is a p-channel field effect transistor.
11. The light emitting driver of claim 10 , wherein the second transistor and the third transistor are p-channel field effect transistors.
12. The light emitting driver of claim 10 , wherein the clock signal is transmitted to the output terminal as a voltage of a logic low level.
13. The light emitting driver of claim 8 , wherein the second transistor includes:
the gate electrode connected to the node;
one terminal connected to the input terminal of the clock signal; and
another terminal connected to the output terminal.
14. The light emitting driver of claim 13 , further comprising a capacitor including one terminal connected to the node and another terminal connected to the another terminal of the second transistor.
15. The light emitting driver of claim 14 , wherein the capacitor is charged by the output signal of the previous arranged scan driving block or the scan start signal, and the second transistor and the third transistor are turned on by a voltage charged to the capacitor.