IP Library Granted Patent US 8,219,733
Granted Patent B2
US 8,219,733 · App. 13/191,958 · Granted Jul 10, 2012

Electronic device with card interface

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,219,733
App. No.
13/191,958
Granted
Jul 10, 2012
Kind
B2
Abstract

When initializing a device, an operation mode of the device is acquired and stored by a predetermined procedure using a predetermined pin. In response to a command, the device executes a signal assignment on a plurality of data pins peculiar to an operation mode indicated by the received command, thereby switching a data transfer width, and allowing the device to operate in the operation mode designated by the received command.

Claims (25)

1. A system for operating a non-volatile programmable memory, the system comprising:

a connector including data pins, a command pin, and a power signal pin, the power signal pin configured to receive an initial power voltage;

means for receiving a first command for reading operation mode information of the system appearing via the command pin, the operation mode information including bus width information which indicates one of first and second operation modes of the system;

means for transmitting the operation mode information via the connector in response to the first command;

means for receiving data via one of the data pins in the first operation mode;

means for receiving data via four of the data pins in the second operation mode;

means for receiving via the command pin a second command for reading operation voltage information;

means for transmitting via the command pin the operation voltage information in response to the second command; and

means for receiving via the command pin a third command for setting an operation mode of the system into one of the first and second operation modes.

2. The system according to claim 1 , further comprising:

means for receiving power voltage information concerning a new power voltage, the new power voltage supplied via the power signal pin.

3. The system according to claim 2 , further comprising means for transmitting a response if the system can operate with the new power voltage.

4. The system according to claim 2 , wherein the initial power voltage differs from the new power voltage.

5. The system according to claim 1 , further comprising:

means for receiving via the command pin a fourth command for reading an address assigned to the system; and

means for transmitting the address via the command pin in response to the fourth command.

6. The system according to claim 5 , further comprising:

means for receiving a fifth command for selecting the system; and

means for shifting the system to a selected state if the address indicated in the fifth command is identical to the address assigned to the system.

7. The system according to claim 1 , further comprising:

means for receiving via the command pin a fourth command for reading identification data unique to the system; and

means for transmitting the identification data via the command pin in response to the fourth command.

8. The system according to claim 7 , wherein the system shifts from a ready state to an identification state after transmitting the identification data.

9. The system according to claim 1 , further comprising:

means for setting the operation mode of the system in response to the third command.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043151/0011 →
Priority Claims (1)
JP 2000-063884 · Mar 8, 2000 · national
Continuity (7)
Continuation 12836195 · Jul 14, 2010
Continuation 11798582 · May 15, 2007
Continuation 11600776 · Nov 17, 2006
Continuation 11366379 · Mar 3, 2006
Continuation 11001309 · Dec 2, 2004
Continuation 09799600 · Mar 7, 2001
Related Publication 20110283024A1 · Nov 17, 2011