Multi-pass system and method supporting multiple streams of video
View Patent ↗Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.
1. A method for data processing, the method comprising:
routing, in real time, a first data stream to a first plurality of processing nodes to generate a second data stream;
routing, in real time, the first data stream and the second data stream to a second plurality of processing nodes to generate a third data stream; and
routing, in real time, one or both of the second data stream and the third data stream to the first plurality of processing nodes to generate a fourth data stream,
wherein a processing node is controlled according to an instruction, and
wherein a DMA controller is adapted to fetch the instruction from a register update list and provide the instruction to a routing node to control routing of a data stream amongst the processing nodes.
2. The method of claim 1 , wherein the first data stream is a video input.
3. The method of claim 1 , wherein the data stream may be stored in memory.
4. The method of claim 1 , wherein the DMA controller provides memory access to the processing node.
5. The method of claim 1 , wherein the third data stream a video output.
6. The method of claim 1 , wherein routing the data stream creates a processing pipeline between at least two processing nodes.
7. A system for data processing, the system comprising:
a first plurality of processing nodes operable to receive a first data stream and generate a second data stream;
a second plurality of processing nodes operable to receive the first data stream, receive the second data stream, and generate a third data stream;
a first routing node operable to route, in real time, the first data stream and the second data stream to the second plurality of processing nodes;
a second routing node operable to route, in real time, the second data stream and the third data stream to the first plurality of processing nodes; and
a DMA controller is operable to fetch an instruction from a register update list and provide the instruction to a routing node to control routing of a data stream amongst the processing nodes.
8. The system of claim 7 , wherein the first data stream is a video input.
9. The system of claim 7 , wherein the data stream may be stored in memory.
10. The system of claim 7 , wherein the DMA controller is operable to provide memory access to the processing node.
11. The system of claim 7 , wherein the third data stream is a video output.
12. The system of claim 7 , wherein the DMA controller is operable to adaptively control the first routing node and the second routing node.
13. The system of claim 7 , wherein the routing node creates a processing pipeline between at least two processing nodes.
14. A multi-media display device comprising:
a first plurality of processing nodes operable to receive a video input and generate a first plurality of data streams;
a second plurality of processing nodes operable to receive the first plurality of data streams and generate a second first plurality of data streams;
a first routing node operable to route, in real time, the first data stream and the second data stream to the second plurality of processing nodes, wherein the first routing node creates a processing pipeline between at least one processing node in the first plurality of processing nodes and at least one processing node in the second plurality of processing nodes;
a second routing node operable to route, in real time, the second data stream and the third data stream to the first plurality of processing nodes, wherein the second routing node creates a processing pipeline between at least one processing node in the first plurality of processing nodes and at least one processing node in the second plurality of processing nodes; and
a DMA controller operable to provide memory access to the first plurality of processing nodes, provide memory access to the second plurality of processing nodes, control the first routing node and control the second routing node,
wherein the DMA controller is operable to fetch an instruction from a register update list and provide the instruction to a routing node to configure the processing pipeline.