Leadless package for high current devices
View Patent ↗Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.
1. A semiconductor package comprising:
a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound;
a first semiconductor device attached to a top side of said paddle portion and enclosed by said mold compound;
a second semiconductor device attached to a bottom side of said paddle portion and in electrical contact with said first semiconductor device;
said extended contact lead frame portion being in direct electrical contact with said second semiconductor device without using a bond wire; and
a thickness of said paddle portion less than a thickness of said first contact lead frame portion.
2. The semiconductor package of claim 1 , further comprising a printed circuit board (PCB) attached to a bottom side of said second semiconductor device.
3. The semiconductor package of claim 1 , wherein the first semiconductor device is a control integrated circuit (IC).
4. The semiconductor package of claim 1 , wherein the second semiconductor device is a power transistor.
5. The semiconductor package of claim 4 , wherein a gate terminal of said power transistor is in direct electrical contact with said extended contact lead frame portion.
6. A semiconductor package comprising:
a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion;
a control IC attached to a top side of said paddle portion;
a power transistor attached to a bottom side of said paddle portion and in electrical contact with said control IC;
said extended contact lead frame portion being in direct electrical contact with said power transistor; and
a thickness of said paddle portion less than a thickness of said first contact lead frame portion.
7. The semiconductor package of claim 6 , further comprising a printed circuit board (PCB) attached to a bottom side of said power transistor.
8. The semiconductor package of claim 6 , wherein a gate terminal of said power transistor is in direct electrical contact with said extended contact lead frame portion.
9. The semiconductor package of claim 6 , wherein said first contact lead frame portion, said paddle portion, and said extended contact lead frame portion are held together by a mold compound.
10. The semiconductor package of claim 9 , wherein said control IC is attached to said top side of said paddle portion and is enclosed by said mold compound.
11. The semiconductor package of claim 6 , wherein said extended contact lead frame portion is in direct electrical contact with said power transistor without using a bond wire.
12. The semiconductor package of claim 6 , wherein said extended contact lead frame portion is in direct electrical contact with said power transistor without using a conductive clip.