Method for manufacturing a liquid crystal display
View Patent ↗A method of manufacturing a liquid crystal display includes: forming a gate line including a gate electrode on a first substrate; forming a gate insulating layer on the gate line; sequentially forming a semiconductor layer, an amorphous silicon layer, and a data metal layer on the entire surface of the gate insulating layer; aligning the edges of the semiconductor layer and the data metal layer; forming a transparent conductive layer on the gate insulating layer and the data metal layer; forming a first pixel electrode and a second pixel electrode by patterning the transparent conductive layer; and forming a data line including a source electrode, a drain electrode, and an ohmic contact layer by etching the data metal layer and the amorphous silicon layer, using the first pixel electrode and the second pixel electrode as a mask, and exposing the semiconductor between the source electrode and the drain electrode.
1. A method of manufacturing a liquid crystal display, comprising:
forming a gate line including a gate electrode on a substrate;
forming a gate insulating layer on the gate line;
sequentially forming a semiconductor layer, an amorphous silicon layer, and a data metal layer on the entire surface of the gate insulating layer;
aligning the edges of the semiconductor layer and the data metal layer by etching the semiconductor layer, the amorphous silicon layer, and the data metal layer;
forming a transparent conductive layer on the gate insulating layer and the data metal laver;
forming a first pixel electrode and a second pixel electrode by patterning the transparent conductive layer;
forming a data line including a source electrode, a drain electrode, and an ohmic contact layer by etching the data metal layer and the amorphous silicon layer, using the first pixel electrode and the second pixel electrode as a mask, and exposing the semiconductor between the source electrode and the drain electrode;
applying a plasma process to the exposed semiconductor;
forming a nitrified silicon film on the first pixel electrode, the second pixel electrode, and the exposed semiconductor,
forming a spacer on the nitrified silicon film corresponding to the exposed semiconductor, and
forming a buffer layer by etching the nitrified silicon film, using the spacer as a mask,
wherein the first pixel electrode is in contact with the drain electrode and the second pixel electrode is in contact with the source electrode.
2. The method of claim 1 , wherein the plasma process is performed by using a gas mixture of a hydrogen gas and a nitrogen gas, under a 250° C. condition.
3. The method of claim 2 , wherein the mixing ratio of the hydrogen gas and the nitrogen gas is 1:1 or more.
4. The method of claim 3 , wherein the mixing ratio of the hydrogen gas and the nitrogen gas is 1:3.
5. The method of claim 4 , further comprising:
forming a passivation layer between the gate insulating layer and the data line, and between the first pixel electrode and the second pixel electrode,
wherein the passivation layer exposes the source electrode and the drain electrode.
6. The method of claim 5 , wherein the aligning of the ends of the semiconductor layer and the data metal layer further includes performing an etch back process before etching the semiconductor layer, after etching the amorphous silicon layer and the data metal layer.
7. The method of claim 6 , wherein the etching solution for etching the transparent conductive layer and the etching solution for etching the data metal layer and the amorphous silicon layer are the same.
8. The method of claim 7 , wherein the data line and the drain electrode comprise a lower layer, the lower layer including at least one of molybdenum, molybdenum-based metal, molybdenum nitride, molybdenum-niobium, molybdenum-vanadium, molybdenum-titanium, and molybdenum-tungsten, an intermediate layer, the intermediate layer including at least one of aluminum, aluminum-based metal, and aluminum-neodymium, and an upper layer, the upper layer including at least one of molybdenum, molybdenum-based metal, molybdenum nitride, molybdenum-niobium, molybdenum-vanadium, molybdenum-titanium, and molybdenum-tungsten.
9. The method of claim 7 , wherein the data line and the drain electrode comprise a lower layer including at least one of titanium and a titanium alloy, and an upper layer including at least one of copper and a copper alloy.
10. The method of claim 1 , wherein the first pixel electrode is in contact with the gate insulating layer, and
the second pixel electrode extends above the data line, in contact with the data line.
11. The method of claim 1 , further comprising:
forming a passivation layer between the gate insulating layer and the data line and between the first pixel electrode and the second pixel electrode,
wherein the passivation layer exposes the source electrode and the drain electrode.
12. The method of claim 11 , wherein the aligning of the edges of the semiconductor layer and the data metal layer further includes performing an etch back process before etching the semiconductor layer, after etching the amorphous silicon layer and the data metal layer.
13. The method of claim 12 , wherein the etching solution for etching the transparent conductive layer and the etching solution for etching the data metal layer and the amorphous silicon layer are the same.
14. The method of claim 1 , wherein the aligning of the ends of the semiconductor layer and the data metal layer further includes performing an etch back process before etching the semiconductor layer, after etching the amorphous silicon layer and the data metal layer.
15. The method of claim 14 , wherein the etching solution for etching the transparent conductive layer and the etching solution for etching the data metal layer and the amorphous silicon layer are the same.
16. The method of claim 1 , wherein the semiconductor layer is an oxide semiconductor.