IP Library Granted Patent US 8,487,421
Granted Patent B2
US 8,487,421 · App. 13/195,187 · Granted Jul 16, 2013

Microelectronic package with stacked microelectronic elements and method for manufacture thereof

Inventors: Hiroaki Sato (Yokohama, JP); Norihito Masuda (Yokohama, JP); Belgacem Haba (Saratoga, CA); Ilyas Mohammed (Santa Clara, CA)
Assignee: Tessera, Inc.
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Quick Facts
Patent No.
US 8,487,421
App. No.
13/195,187
Granted
Jul 16, 2013
Kind
B2
Abstract

A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact.

Claims (63)

1. A microelectronic package, the package having a top surface and a bottom surface remote from the top surface, the package comprising:

a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing the top surface and a rear face remote from the front face, wherein the front face of the first microelectronic element is adjacent the top surface, wherein the first microelectronic element overlies the front face of the second microelectronic element such that at least a portion of the front face of the second microelectronic element having at least one element contact thereon extends beyond an edge of the first microelectronic element;

an encapsulant between the top surface and the front face of the second microelectronic element;

at least one first package terminal at the top surface, the first terminal usable to connect the package to a contact of a first microelectronic component external to the package; and

a conductive structure electrically connecting the first terminal to the at least one element contact at the front face of the second microelectronic element, the conductive structure including a continuous monolithic metal feature extending along the top surface and through at least a portion of the encapsulant towards the at least one element contact.

2. The package of claim 1 , wherein the metal feature is formed by electrolytic metal deposition.

3. The package of claim 1 , wherein the conductive structure further includes a first metal layer extending along the top surface from the first terminal, the first metal layer and the metal feature being electrically connected through a metallized via.

4. The package of claim 3 , wherein the metallized via directly connects the first metal layer with the metal feature.

5. The package of claim 3 , wherein the metal feature includes the metallized via.

6. The package of claim 1 further comprising:

at least one second package terminal at the bottom surface, the second terminal usable to connect the package to a contact of a second microelectronic component external to the package,

wherein the conductive structure includes a conductive via extending through the encapsulant electrically connecting the first terminal with the second terminal.

7. The package of claim 1 , wherein the first and second microelectronic elements are adhesively attached to each other.

8. The package of claim 1 , wherein the monolithic metal feature includes a conductive via extending from the top surface through a portion of the encapsulant towards the at least one element contact and a conductive trace extending along the top surface away from the conductive via.

9. The package of claim 8 , wherein the conductive via and the conductive trace are formed simultaneously.

10. The package of claim 8 , wherein the conductive trace is connected to the conductive via without solder.

11. The package of claim 8 , wherein the conductive trace and the conductive via are formed from a conductive paste.

12. The package of claim 1 further comprising:

a solder mask at the top surface, the first terminal being uncovered by the solder mask.

13. The package of claim 1 further comprising:

a solder mass joined to a surface of the first terminal.

14. The package of claim 1 , wherein the encapsulant has a molded planar surface such that the top surface is planar.

15. The package of claim 1 , wherein the conductive structure includes a plurality of conductive materials.

16. The package of claim 1 , wherein the encapsulant is between the top surface and the bottom surface.

17. The package of claim 1 , wherein the first microelectronic component external to the package is a circuit panel.

18. A microelectronic assembly including the package of claim 17 further comprising the circuit panel having the contact thereon, and a conductive mass joining the terminal of the package with the contact of the circuit panel.

19. A microelectronic assembly comprising first and second microelectronic packages of claim 1 vertically stacked with the respective bottom surfaces facing each other,

the assembly further comprising a conductive via extending through the encapsulants, respectively, of the first and second microelectronic packages and electrically connecting the first terminal of the first package with the first terminal of the second package.

20. A microelectronic assembly comprising first and second microelectronic packages of claim 1 vertically stacked with the bottom surface of the first microelectronic package facing the top surface of the second microelectronic package,

the assembly further comprising a solder mass extending between the first and second microelectronic packages and electrically connecting the first terminal of the first microelectronic package with the first terminal of the second microelectronic package.

21. A microelectronic assembly comprising first and second microelectronic packages of claim 1 vertically stacked with the bottom surface of the first microelectronic package facing the top surface of the second microelectronic package,

the assembly further comprising a wire bond extending from the first terminal of the first microelectronic package, over an edge of the first microelectronic package and to the second terminal of the second microelectronic package.

22. A microelectronic package, the package having a top surface and a bottom surface remote from the top surface, the package comprising:

a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing the top surface and a rear face remote from the front face, wherein the front face of the first microelectronic element is adjacent the top surface, wherein the first microelectronic element overlies the front face of the second microelectronic element such that at least a portion of the front face of the second microelectronic element having at least one element contact thereon extends beyond an edge of the first microelectronic element;

an encapsulant between the top surface and the front face of the second microelectronic element;

at least one package terminal at the top surface, the terminal usable to connect the package to a contact of a microelectronic element external to the package; and

a conductive structure electrically connecting the terminal to the at least one element contact at the front face of the second microelectronic element, the conductive structure including a wire bond extending from the at least one element contact, through the encapsulant and to the top surface and a conductive trace contacting the wire bond and extending along the top surface away from the wire bond.

23. The package of claim 22 , wherein the trace is formed by electrolytic metal deposition.

24. The package of claim 22 , wherein the trace is formed of at least one of conductive paste or conductive matrix material.

25. A microelectronic package, the package having a top surface and a bottom surface remote from the top surface, the package comprising:

a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing the top surface and a rear face remote from the front face, wherein the rear face of the second microelectronic element is adjacent the bottom surface, wherein the first microelectronic element overlies the front face of the second microelectronic element such that at least a portion of the front face of the second microelectronic element having at least one element contact thereon extends beyond an edge of the first microelectronic element;

a substrate having a first surface and a second surface, wherein the stacked unit overlies the first surface of the substrate such that at least a portion of the first surface having at least one substrate contact thereon extends beyond an edge of the stacked microelectronic unit;

an encapsulant covering at least a portion of the stacked unit and the first surface of the substrate;

at least one first package terminal at the top surface and electrically connected to the substrate contact; and

at least one second package terminal at the second surface of the substrate and electrically connected to the substrate contact; and

a conductive structure electrically connecting the first terminal with the substrate contact and at least one first element contact of an element contact at the front face of the first microelectronic element or the at least one element contact at the front face of the second microelectronic element, the conductive structure including a continuous monolithic metal feature extending through the encapsulant towards the at least one first element contact and the substrate contact.

26. The package of claim 25 , wherein the monolithic metal feature includes (i) a conductive via extending from the top surface through the encapsulant towards the least one element contact and (ii) a conductive trace extending at the top surface and electrically connecting the conductive via with the substrate contact.

27. The package of claim 25 , wherein the conductive vias and the conductive traces are formed simultaneously.

28. The package of claim 25 , wherein the conductive structure includes a connection element electrically connecting the element contact of the first microelectronic element to the substrate contact, the connection element not being electrically connected to any other element contact of the stacked unit.

29. The package of claim 25 , wherein the conductive structure electrically connects element contacts respectively on the front faces of the first and second microelectronic elements to each other.

30. A method of fabricating a microelectronic package comprising:

providing a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face and a rear face remote from the front face, wherein the front face of the first microelectronic element is attached to a carrier element, wherein the front face of the second microelectronic element overlies the rear face of the first microelectronic element such that at least a portion of the front face of the second microelectronic element having at least one element contact thereon extends beyond an edge of the first microelectronic element;

forming an encapsulant between the carrier element and the front face of the second microelectronic element;

forming at least one first package terminal overlying the front surface of the first microelectronic element or a portion of the encapsulant beyond the front surface of the first microelectronic element; and

forming a conductive structure extending through the encapsulant electrically connecting the at least one first package terminal to the at least one element contact at the front face of the second microelectronic element, wherein the at least one first package terminal is exposed at a top surface of the package.

31. The method of claim 30 , wherein the first terminal is usable to connect the package to a contact of a first microelectronic component external to the package.

32. The method of claim 30 , wherein the conductive structure includes a continuous monolithic metal feature extending along the top surface and through at least a portion of the encapsulant towards the at least one element contact.

33. The method of claim 30 , wherein the encapsulant is formed to have a surface at a bottom surface of the package remote from the top surface.

34. The method of claim 33 further comprising:

forming at least one second package terminal at a bottom surface of the package remote from the top surface, the second terminal being usable to connect the package to a contact of a second microelectronic component external to the package, wherein a second conductive structure extends through the encapsulant electrically connecting the first terminal with the second terminal.

35. The method of claim 34 , wherein the encapsulant is formed to have a surface at the bottom surface of the package.

36. The method of claim 30 further comprising:

removing the carrier element.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0373 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0816 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2011
From: SATO, HIROAKI; MASUDA, NORIHITO; HABA, BELGACEM; MOHAMMED, ILYAS
To: TESSERA, INC.
Reel/Frame 027139/0875 →
Continuity (1)
Related Publication 20130032944A1 · Feb 7, 2013