An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A capacitance is provided having a first node connected to an input terminal of the control circuit. A display signal voltage generation circuit generates display signal voltages for the pixels, while a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. In addition, a connector is provided for connecting either one of the display signal voltages or the pixel drive voltages to a second node of the capacitance.
1. An image display device comprising: an image displaying area including a plurality of pixels with an OLED, including one terminal which has been grounded, said pixels being formed in a matrix form;
a signal drive circuit for generating a display signal voltage to be supplied to the plurality of pixels;
a signal line connected between each of pixels through which the display signal voltage is inputted to each of pixels;
a first voltage line connected between each of pixels through which a first voltage is supplied to each of pixels;
a second voltage line connected between each of pixels through which a second voltage is supplied to each of pixels;
a drive TFT, a drain terminal of which is configured to be connected to another terminal of the OLED, and a source terminal of which is configured to be connected to the first voltage line;
a reset TFT, one terminal of which is connected to a gate terminal of the drive TFT, and another terminal of which is connected to the drain terminal of the drive TFT;
a memory capacitor, a first terminal of which is connected to a gate terminal of the drive TFT;
an input TFT, one terminal of which is connected to a second terminal of the memory capacitor, and another terminal of which is connected to the signal line; and
a drive input TFT, one terminal of which is connected to the first terminal of the memory capacitor, and another terminal of which is connected to the second voltage line;
wherein each of gates of the reset TFT, the input TFT and the drive input TFT is configured to be controlled by a device outside of the plurality of pixels.
2. The image display device according to claim 1 , wherein the drive TFT comprises a P-MOS type transistor.
3. The image display device according to claim 1 , wherein the second voltage line and the signal line are provided in parallel.
4. The image display device according to claim 1 , wherein the first voltage line and the signal line are provided in parallel.
5. The image display device according to claim 1 , wherein each of lines for controlling the reset TFT, the input TFT and the drive input TFT is provided in parallel with each other.
6. The image display device according to claim 1 , wherein an amount of resistor and of the signal line is smaller than an amount of resistor and of each of the lines for controlling the reset TFT, the input TFT and the drive input TFT.
7. The image display device according to claim 2 , wherein the first voltage line comprises a P-channel source line, and the second voltage line comprises a drive signal line.