Amorphous semiiconductor layer memory device
View Patent ↗A memory device includes: an amorphous semiconductor layer of a first conduction type; a solid electrolyte layer containing movable ions and provided in contact with a part of one of faces of the amorphous semiconductor layer; a first electrode electrically connected to the amorphous semiconductor layer via the solid electrolyte layer; a second electrode electrically connected to one of the faces of the amorphous semiconductor layer; and a third electrode provided over the other face of the amorphous semiconductor layer with an insulating layer therebetween. At the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type.
1. A memory device comprising:
a first electrode;
a first insulating layer stacked on the first electrode;
an amorphous semiconductor layer of a first conduction type stacked on the first insulating layer;
a solid electrolyte layer containing movable ions stacked on and in contact with a part of one face of the amorphous semiconductor layer;
a second electrode stacked on and electrically connected to the amorphous semiconductor layer via the solid electrolyte layer;
a third electrode stacked on and electrically connected to another part of the one face of the amorphous semiconductor layer;
a second insulating layer stacked on the one face of the amorphous semiconductor layer and between the second and third electrodes; and
wherein,
at the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type.
2. The memory device according to claim 1 , wherein at the time of application of voltage to the first electrode, an accumulation layer is formed on the amorphous semiconductor layer and, by movement of movable ions from the solid electrolyte layer to the amorphous semiconductor layer, the conduction type of the amorphous semiconductor layer changes.
3. The memory device according to claim 1 , wherein magnitude of a resistance value between the second and third electrodes can be controlled by adjusting magnitude and time of voltage applied across the second and third electrodes.
4. The memory device according to claim 3 , wherein at least one bit can be stored by controlling the magnitude of the resistance value.
5. The memory device according to claim 1 , wherein trap concentration in the amorphous semiconductor layer is equal to or higher than a donor concentration or an acceptor concentration.
6. The memory device according to claim 1 , wherein:
A temperature at which the movable ions contained in the solid electrolyte layer become movable is 300 degrees Kelvin or higher, and
a concentration of the movable ions in the solid electrolyte layer at 300 degrees Kelvin is equal to or less than a trap concentration of the amorphous semiconductor layer.
7. A memory device comprising:
an amorphous semiconductor layer of a first conduction type;
a solid electrolyte layer containing movable ions and provided in contact with a part of one face of the amorphous semiconductor layer;
a first electrode electrically connected to the amorphous semiconductor layer via the solid electrolyte layer;
a second electrode electrically connected to the one face of the amorphous semiconductor layer;
a heat barrier layer provided between the first electrode and the solid electrolyte layer, between the second electrode and the amorphous semiconductor layer, or both; and
a third electrode provided over another face of the amorphous semiconductor layer with an insulating layer therebetween,
wherein,
at the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type.
8. A memory device comprising:
an amorphous semiconductor layer of a first conduction type;
a solid electrolyte layer containing movable ions and provided in contact with a part of one face of the amorphous semiconductor layer;
a first electrode electrically connected to the amorphous semiconductor layer via the solid electrolyte layer;
a second electrode electrically connected to the one face of the amorphous semiconductor layer; and
a third electrode provided over another face of the amorphous semiconductor layer with an insulating layer therebetween,
wherein,
at the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type, and
the amorphous semiconductor layer contains a chalcogen element (S, Se, Te) or an alloy of the chalcogen element.
9. A memory device comprising:
an amorphous semiconductor layer of a first conduction type;
a solid electrolyte layer containing movable ions and provided in contact with a part of one face of the amorphous semiconductor layer;
a first electrode electrically connected to the amorphous semiconductor layer via the solid electrolyte layer;
a second electrode electrically connected to the one face of the amorphous semiconductor layer; and
a third electrode provided over another face of the amorphous semiconductor layer with an insulating layer therebetween,
wherein,
at the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type, and
the amorphous semiconductor layer is made of Ge X Te 100-X (10≦X≦60).
10. The memory device of claim 1 , further comprising a heat barrier layer between the second electrode and the solid electrolyte layer, between the third electrode and the amorphous semiconductor layer, or both.