Thin film transistor array substrate and manufacturing method thereof
View Patent ↗A thin film transistor array substrate includes a gate line disposed on a substrate, the gate line comprising a gate electrode including a lower film and an upper film thicker than the lower film, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer formed on the semiconductor layer, a data line electrically connected to a source electrode and a drain electrode formed on the ohmic contact layer, the lower film of the gate line is in contact with the gate insulating layer at a crossing portion of the gate line and the data line and the heights of the source electrode and the drain electrode are substantially the same as or less than a height of the semiconductor layer.
1. A method of manufacturing a thin film transistor array substrate, the method comprising:
forming a gate line disposed on a substrate, the gate line comprising a gate electrode;
forming a gate insulating layer over the gate electrode;
forming a semiconductor layer over the gate insulating layer;
forming an ohmic contact layer over the semiconductor layer;
forming a data layer over the ohmic contact layer;
depositing a photoresist layer on the data layer;
forming a data line, a source electrode, and a drain electrode using the photoresist as a mask; and
removing the photoresist on the source electrode and the drain electrode, wherein the gate line at a crossing portion of the gate line and the data line is thinner than the gate electrode.
2. The method of claim 1 , further comprising:
controlling a height of the photoresist to be substantially the same as a height of the semiconductor layer by decreasing a thickness of the photo resist; and
etching a portion of data line and the ohmic contact layer between the source electrode and drain electrode.
3. The method of claim 1 , wherein planar shapes of the semiconductor layer and the ohmic contact layer are substantially the same as the data line, the source electrode and the drain electrode.
4. The method of claim 1 , wherein the gate line includes a lower film and an upper film thicker than the lower film and the gate line includes the lower film and the upper film.
5. The method of claim 4 , wherein the gate line contacts the gate insulating layer at the crossing portion.
6. The method of claim 4 , wherein a thickness of the data line at the crossing portion of the gate line and the data line is d, a thickness of the ohmic contact layer is n, and a thickness of the upper film of the gate line is t, and d, n and t have the following relation:
d+n<t.
7. The method of claim 4 , wherein the semiconductors layer, the ohmic contact layer and the data line are formed by a single photoresist coating process.
8. The method of claim 1 , further comprising:
forming a passivation layer on the data line;
forming a contact hole in the passivation layer; and
forming a pixel electrode electrically connected to the drain electrode through the contact hole.
9. The method of claim 8 , wherein the passivation layer comprises at least one of an organic material and color filter material.
10. The method of claim 8 , wherein the pixel electrode overlaps with the semiconductor layer.
11. The method of claim 1 , wherein the gate electrode has a taper angle of about 30 to about 80 degrees.
12. The method of claim 1 , wherein the source electrode and the drain electrode overlap with the gate electrode on a sidewall of the gate electrode.