Multiple circuit blocks with interblock control and power conservation
View Patent ↗A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.
1. A semiconductor integrated circuit comprising:
a power source line;
a first circuit block configured to output a data signal;
a power source switch controllable to allow or to cut off supply of a power supply voltage from the power source line to the first circuit block, the power supply voltage being applied to the first circuit block in a first mode and stopped from being applied to the first circuit block in a second mode;
a storage unit configured to receive the data signal output from the first circuit block, store and transmit the data signal output from the first circuit block in response to receiving the data signal, and transmit the data signal stored by the storage unit when not receiving the data signal from the first circuit block;
a signal gate unit controllable to allow or to interrupt transmission of the data signal from the first circuit block to the storage unit; and
an output buffer configured to receive the data signal transmitted from the storage unit and output the data signal to a pad,
wherein the signal gate unit supplies the data signal to the storage unit in the first mode and the signal gate unit does not supply the data signal to the storage unit in the second mode.
2. A semiconductor integrated circuit, comprising:
a first circuit block to which a first power supply voltage is applied in a first mode and stopped from being applied in a second mode;
a second circuit block to which a second power supply voltage is applied; and
a third circuit block to which a third power voltage is applied and including a first storage unit and a first signal gate unit provided between the first storage unit and the first circuit block, and wherein
the first storage unit is configured to receive a first signal output from the first circuit block, hold and output the first signal output from the first circuit block in response to receiving the first signal, and output the first signal held by the first storage unit when not receiving the first signal from the first circuit block,
upon being output from the first storage unit, the first signal is input to the second circuit block,
the second circuit block includes an output buffer configured to output the first signal input to the second circuit block to a pad, and
the first signal gate unit supplies the first signal to the first storage unit in the first mode and the first signal gate unit does not supply the first signal to the first storage unit in the second mode.
3. The semiconductor integrated circuit according to claim 2 , wherein the third power supply voltage is equal to the first power supply voltage and the second power supply voltage is higher than the first power supply voltage, and wherein the second circuit block includes a level conversion circuit for converting a signal level from amplitude of the third power supply voltage to amplitude of the second power supply voltage.
4. The semiconductor integrated circuit according to claim 2 , wherein:
the third circuit block includes a second storage unit and a second signal gate unit provided between the second storage unit and the first circuit block,
the second storage unit is configured to receive a second signal output from the first circuit block, hold and output the second signal output from the first circuit block in response to receiving the second signal, and output the second signal held by the second storage unit when not receiving the second signal from the first circuit block,
upon being output from the second storage unit, the second signal is input to the second circuit block,
the second signal gate unit supplies the second signal to the second storage unit in the first mode and the second signal gate unit does not supply the second signal to the second storage unit in the second mode, and
the second signal input to the second circuit block enables the output buffer to output the first signal input to the second circuit block to the pad.