Method of forming trench isolation
A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure.
1. A method of forming trench isolation of a semiconductor device, comprising:
providing a semiconductor substrate formed thereon a first mask layer;
performing a first etching process with the first mask layer as an etching mask to form a shallow trench structure;
applying a first dielectric material to fill the shallow trench structure while forming a first dielectric layer on the semiconductor substrate as well as on the first mask layer;
patterning the first dielectric layer to form a second mask layer;
performing a second etching process with the second mask layer as an etching mask to form a deep trench structure; and
applying a second dielectric material to fill the deep trench structure while forming a second dielectric layer on the semiconductor substrate as well as on the second mask layer, wherein the second dielectric layer is contacted with the second mask layer.
2. The method as claimed in claim 1 further comprising performing a chemical mechanical polishing (CMP) process for planarization.
3. The method as claimed in claim 1 wherein the shallow trench structure is formed in an area of the semiconductor substrate corresponding to a logic region and the deep trench structure is formed in another area of the semiconductor substrate corresponding to a pixel region.
4. The method as claimed in claim 3 wherein the deep trench structure is configured to isolate sensor devices in the pixel region.
5. The method as claimed in claim 1 , wherein the first mask layer is a silicon nitride layer.
6. The method as claimed in claim 1 , wherein the second mask layer is a silicon oxide layer.
7. The method as claimed in claim 1 , wherein the shallow trench structure has a depth in a range of 2000 to 4000 angstroms.
8. The method as claimed in claim 1 , wherein the deep trench structure has a depth in a range of 20000 to 40000 angstroms.
9. The method as claimed in claim 1 , further comprising forming a first liner layer inside the shallow trench structure before applying the first dielectric material to fill the shallow trench structure.
10. A method of forming trench structures in a semiconductor substrate, comprising:
providing a semiconductor substrate having a first area and a second area adjacent to the first area;
forming a first mask layer disposed on the semiconductor substrate;
performing a first etching process with the first mask layer to form a plurality of first trench structures having a first depth in the first area of the semiconductor substrate;
forming a first dielectric layer on the semiconductor substrate with the first trench structures, the first dielectric layer covering the first area and the second area while filling the first trench structures as well as formed on the first mask layer;
patterning the first dielectric layer to form a second mask layer;
performing a second etching process with the second mask layer to form a plurality of second trench structures having a second depth different from the first depth; and
forming a second dielectric layer covering the first area and the second area of the semiconductor substrate and filling the second trench structures, wherein the second dielectric layer is contacted with the second mask layer.
11. The method as claimed in claim 10 , wherein the first depth is larger than the second depth.
12. The method as claimed in claim 10 , wherein the first depth is less than the second depth.
13. The method as claimed in claim 10 , further comprising performing a chemical mechanical polishing (CMP) process for planarization.
14. The method as claimed in claim 13 wherein the first area is where logic circuit is to be formed.
15. The method as claimed in claim 13 wherein the second area is where sensing circuit is to be formed.