IP Library Granted Patent US 8,693,208
Granted Patent B2
US 8,693,208 · App. 13/205,300 · Granted Apr 8, 2014

PCIe bus extension system, method and interfaces therefor

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Quick Facts
Patent No.
US 8,693,208
App. No.
13/205,300
Granted
Apr 8, 2014
Kind
B2
Abstract

A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port.

Claims (20)

1. In a computer system, a PCIe bus extension system for connecting a PCIe-compliant peripheral device to a PCIe bus of the computer system, the extension system comprising:

a PCIe interface card within an enclosure of the computer system, the PCIe interface card having at least one interface port and an edge connector configured to interface with a PCIe expansion slot, the edge connector being functionally connected with a PCIe expansion slot on a motherboard within the enclosure, the PCIe interface card having a logic integrated circuit that functionally connects PCIe signals transmitted from the motherboard to the interface port and functionally connects PCIe signals transmitted from the interface port to the motherboard;

a PCIe-compliant peripheral device having an interface port that is functionally identical to the interface port on the PCIe interface card but with a mirror-symmetric pin out to receive clock and data signals from the PCIe interface card and to send data signals to the PCIe interface card;

a cable connecting the interface port of the PCIe interface card to the interface port of the PCIe-compliant peripheral device, the cable being configured for complete crossover of all of the PCIe signals, the cable being adapted to transfer multiple parallel lanes of the PCIe signals as a single channel in full duplex mode;

wherein the PCIe-compliant peripheral device does not receive power through the PCIe interface card, further comprising a PCIe switch that arbitrates between the clock and data signals of the multiple parallel PCIe lanes over the channel and additional clock and data signals of additional multiple parallel PCIe lanes over at least one additional channel provided by at least one additional cable.

2. The PCIe bus extension system of claim 1 , wherein the PCIe interface card comprises a re-driver circuit and a zero-delay clock buffer adapted to amplify and forward the clock and data signals to the interface port.

3. The PCIe bus extension system of claim 1 , wherein the interface port on the PCIe interface card and the interface port on the peripheral device are mini-SAS 4i connectors and the channel comprises four PCIe lanes.

4. The PCIe bus extension system of claim 1 , wherein the edge connector of the PCIe interface card is physically connected to the PCIe expansion slot on the motherboard.

5. The PCIe bus extension system of claim 1 , wherein the edge connector of the PCIe interface card is functionally connected to the PCIe expansion slot on the motherboard through a PCIe riser card within the enclosure.

6. A PCIe interface card for a PCIe bus of a computer system, the PCIe interface card comprising:

a printed circuit board; an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the PCIe interface card;

an interface port configured to mate with a connector of a cable; and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data signals of the PCIe signals there between that are compliant with a PCIe standard;

wherein the PCIe interface card is adapted to transfer multiple parallel lanes of the PCIe signals over a cable as a single channel in full duplex mode, and the PCIe interface card lacks means for transmitting power there through to a PCIe-compliant peripheral device connected to the PCIe interface card through the interface port,

Further comprising a PCIe switch adapted to arbitrate between the clock and data signals of the multiple parallel PCIe lanes over the channel and additional clock and data signals of additional multiple parallel PCIe lanes over at least one additional channel provided by at least one additional cable.

7. The PCIe interface card of claim 6 , further comprising a re-driver circuit and a zero-delay clock buffer adapted to amplify and forward the clock and data signals to the interface port.

8. The PCIe interface card of claim 6 , wherein the interface port is a mini-SAS 4i connector.

9. The PCIe interface card of claim 6 , wherein the interface port is mated with a connector of a cable configured for complete crossover of all of the PCIe signals.

10. The PCIe interface card of claim 9 , wherein the cable comprises a mini-SAS 4i connector connected to the interface port and the channel comprises four PCIe lanes.

11. The PCIe interface card of claim 10 , wherein the cable connects the PCIe interface card to a solid state drive and PCIe data and clock signals are transmitted between the PCIe interface card and the solid state drive.

12. The PCIe interface card of claim 11 , wherein the solid state drive comprises an array of NAND flash memory devices.

Assignments (16)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 030092/0739) Recorded Apr 8, 2014
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0284 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 031611/0168) Recorded Apr 8, 2014
From: COLLATERAL AGENTS, LLC
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0455 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE AND ATTACH A CORRECTED ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 032365 FRAME 0920. ASSIGNOR(S) HEREBY CONFIRMS THE THE CORRECT EXECUTION DATE IS JANUARY 21, 2014. Recorded Mar 18, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032461/0486 →
CHANGE OF NAME Recorded Feb 27, 2014
From: TAEC ACQUISITION CORP.
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 032365/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032365/0920 →
SECURITY AGREEMENT Recorded Nov 11, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: COLLATERAL AGENTS, LLC
Reel/Frame 031611/0168 →
SECURITY AGREEMENT Recorded Mar 27, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 030092/0739 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 030088/0443 →
SECURITY AGREEMENT Recorded May 14, 2012
From: OCZ TECHNOLOGY GROUP, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 028440/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2011
From: REINKE, KARL; KIM, DOKYUN; ALLEN, WILLIAM J.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 026871/0146 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2011
From: REINKE, KARL; KIM, DOKYUN; ALLEN, WILLIAM J.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 026871/0156 →