Method of fabricating thin film transistor by crystallization through metal layer forming source and drain electrodes
View Patent ↗A method of fabricating a thin film transistor includes patterning the amorphous semiconductor layer to form an amorphous semiconductor layer pattern, forming a gate electrode corresponding to the amorphous semiconductor layer pattern on a gate insulating layer, forming an interlayer insulating layer on the entire surface of the substrate, forming a first contact hole partially exposing the amorphous semiconductor layer pattern, forming a second contact hole partially exposing the gate electrode, and forming a metal layer on the entire surface of the substrate. The method also includes applying an electrical field to the metal layer such that a semiconductor layer is formed by crystallization of the amorphous semiconductor layer pattern, and patterning the metal layer to form source and drain electrodes that are insulated from the gate electrode and that are electrically connected with the semiconductor layer through the first contact hole.
1. A method of fabricating a thin film transistor, comprising:
preparing a substrate;
forming a buffer layer on the substrate;
forming an amorphous semiconductor layer on the buffer layer;
patterning the amorphous semiconductor layer to form an amorphous semiconductor layer pattern;
forming a gate insulating layer on the amorphous semiconductor layer pattern;
forming a gate electrode overlapping the amorphous semiconductor layer pattern on the gate insulating layer;
forming an interlayer insulating layer on the entire surface of the substrate;
patterning the interlayer insulating layer to form first contact holes partially exposing the amorphous semiconductor layer pattern and a second contact hole at least partially exposing the gate electrode on the gate insulating layer;
forming a metal layer on the entire surface of the substrate, the metal layer filling the first contact holes and the second contact hole;
applying an electrical field to the metal layer such that a semiconductor layer is formed by crystallization of the amorphous semiconductor layer pattern; and
after applying the electrical field to the metal layer, patterning the metal layer such that first portions of the metal layer remain in the first contact holes and a second portion remains in the second contact hole, top surfaces of the first portions being aligned with a top surface of the second portion, and the first portions corresponding to source and drain electrodes that are insulated from the gate electrode and that are electrically connected with the semiconductor layer through the first contact holes.
2. The method as claimed in claim 1 , wherein during applying the electrical field, crystallization of the amorphous semiconductor layer pattern is performed while the metal layer is in contact with the gate electrode through the second contact hole.
3. The method as claimed in claim 1 , wherein the electrical field is about 100 V/cm 2 to about 10,000 V/cm 2 .
4. The method as claimed in claim 1 , wherein the metal layer is formed to prevent exposure of the interlayer insulating layer, and the electrical field is applied to the metal layer.
5. The method as claimed in claim 1 , wherein the first contact holes are formed to be spaced apart from the second contact hole.
6. The method as claimed in claim 1 , wherein the second contact hole is formed to correspond to a channel region of the semiconductor layer.
7. The method as claimed in claim 1 , wherein second portion of the metal layer is in direct contact with the gate electrode.
8. The method as claimed in claim 1 , wherein the metal layer is formed on the interlayer insulating layer after patterning the interlayer insulating layer to form the first contact holes and the second contact hole.
9. The method as claimed in claim 1 , wherein during applying the electrical field to the metal layer, heat is transferred from the portions of the metal layer that fill the first contact holes and the second contact hole to the amorphous semiconductor layer pattern.
10. The method as claimed in claim 1 , wherein the source and drain electrodes are composed entirely of the metal layer.
11. The method as claimed in claim 8 , wherein the metal layer is formed directly on the interlayer insulating layer, is formed to be in direct contact with the amorphous semiconductor layer pattern via the first contact holes, and is formed to be in direct contact with the gate electrode via the second contact hole.
12. The method as claimed in claim 11 , wherein the metal layer is formed to cover the interlayer insulating layer such that the metal layer covers the interlayer insulating layer during applying of the electrical field to the metal layer.
13. The method as claimed in claim 1 , wherein the patterning of the amorphous semiconductor layer and the patterning of the interlayer insulating layer are both performed before forming the metal layer on the entire surface of the substrate.
14. The method as claimed in claim 1 , wherein the source and drain electrodes are composed entirely of the metal layer.