Semiconductor device and power supply control method of the semiconductor device

1. A semiconductor device comprising:

an internal circuit;

a power supply control circuit which controls supply of a power supply to the internal circuit, upon receipt of a first control signal; and

a control signal generation circuit which outputs the first control signal, upon receipt of a second control signal; wherein

the control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

2. The semiconductor device according to claim 1 , wherein

the control signal generation circuit includes:

a delay circuit which delays the second control signal, thereby generating a third control signal; and

a combination circuit which activates the first control signal when one of the second control signal and the third control signal is active and deactivates the first control signal when both of the second control signal and the third control signal are inactive.

3. The semiconductor device according to claim 1 , wherein

the power supply control circuit comprises a first power supply switch connected between a first power supply and the internal circuit and controlled to turn on or off by the first control signal, and supplies the first power supply to the internal circuit through the first power supply switch.

4. The semiconductor device according to claim 3 , wherein

the first power supply switch comprises a first field effect transistor of a first conductivity with a source thereof connected to the first power supply, a drain thereof connected to the internal circuit, and a gate thereof connected to the first control signal; and

the control signal generation circuit outputs a voltage having an absolute value higher than a voltage of the first power supply so that the first field effect transistor is sufficiently turned off when the first control signal is in an inactive state.

5. The semiconductor device according to claim 3 , wherein

the internal circuit comprises:

a CMOS transistor circuit including an MOS transistor of a first conductivity and an second conductivity type MOS transistor of a conductivity opposite to the first conductivity; and

the first power supply switch comprises the second conductivity MOS transistor which is source-follower connected, with a drain thereof connected to the first power supply, a source thereof connected to a source of the MOS transistor of the first conductivity of the CMOS transistor circuit, and a gate thereof controlled to turn on or off by the first control signal.

6. The semiconductor device according to claim 1 , wherein

the power supply control circuit comprises:

a first power supply switch connected between a first

power supply and the internal circuit; and

a second power supply switch connected between a second power supply and the internal circuit;

both of the first and second power supply switches are controlled to turn on or off by the first control signal; and

when the first control signal is activated, the first power supply is supplied to the internal circuit through the first power supply switch and the second power supply is supplied to the internal circuit through the second power supply switch.

7. The semiconductor device according to claim 6 , wherein

the internal circuit comprises:

a first gate circuit to which the first power supply is directly supplied without intervention of the first power supply switch and the second power supply is supplied through the second power supply switch when the first control signal is active, an output node potential the first gate circuit being fixed to a potential that is the same as a potential of the first power supply when the first control signal is inactive; and

a second gate circuit to which the first power supply is supplied through the first power supply switch and the second power supply is directly supplied without intervention of the second power supply switch when the first control signal is active, an output node potential of the second gate circuit being fixed to a potential that is the same as a potential of the second power supply when the first control signal is inactive.

8. The semiconductor device according to claim 6 , wherein

the first power supply switch comprises a PMOS power supply switch transistor with a source thereof connected to the first power supply and a drain thereof connected to the internal circuit;

the second power supply switch comprises an NMOS power supply switch transistor with a source thereof connected to the second power supply and a drain thereof connected to the internal circuit;

the first control signal includes a first gate control signal connected to a gate of the PMOS power supply switch transistor and a second gate control signal connected to a gate of the NMOS power supply switch transistor; and

the control signal generation circuit outputs a voltage higher than a voltage of the first power supply as the first gate control signal and outputs a voltage lower than a voltage of the second power supply as the second gate control signal when the first control signal becomes inactive.

9. The semiconductor device according to claim 6 , wherein

the first power supply outputs a higher voltage than the second power supply;

the first power supply switch comprises an NMOS power supply switch transistor with a drain thereof connected to the first power supply and a source thereof connected to the internal circuit;

the second power supply switch comprises a PMOS power supply switch transistor with a drain thereof connected to the second power supply and a source thereof connected to the internal circuit;

the first control signal includes a first gate control signal connected to a gate of the NMOS power supply switch transistor and a second gate control signal connected to a gate of the PMOS power supply switch transistor; and

the control signal generation circuit outputs the first gate control signal as a signal having a same potential as the second power supply and outputs the second gate control signal as a signal having a same potential as the first power supply when the first control signal becomes inactive; and

when the first control signal becomes active, the control signal generation circuit outputs the first gate control signal as a signal having a voltage not less than a voltage of the first power supply and outputs the second gate control signal as a signal having a voltage not more than a voltage of the second power supply.

10. A semiconductor device comprising:

an internal circuit;

a power supply terminal supplied with a power supply voltage; and

a power supply control circuit provided between the power supply terminal and the internal circuit, and receiving a control signal, the control signal changing from an active state to an inactive state, and then returning from the inactive state to the active state;

the power supply control circuit keeping an electrical connection between the power supply terminal and the internal circuit when the control signal is in the active state, maintaining the electrical connection when a period from the changing to the returning is equal to or shorter than a predetermined period, and cutting off the electrical connection when the period from the changing to the returning is longer than the predetermined period.

11. The semiconductor device according to claim 10 , further comprising an external terminal receiving a clock enable signal from outside of the semiconductor device, the control signal changing from the active state to the inactive state when the clock enable signal changes from the active state to the inactive state, and returning from the inactive state to the active state when the clock enable signal returns from the inactive state to the active state.

12. The semiconductor device according to claim 10 , wherein the power supply control circuit includes:

a delay circuit delaying the control signal to produce a first signal;

a logic circuit receiving the control signal and the first signal, and outputting a second signal, the second signal taking an active state when at least one of the control signal and the first signal is in the active state, and taking an inactive state when each of the control signal and the first signal is in the inactive state; and

a power gate transistor coupled between the internal circuit and the power supply terminal, and receiving the second signal at a gate electrode thereof.

13. The semiconductor device according to claim 12 , wherein the power gate transistor includes a first conductive type transistor, the power supply control circuit further includes an additional power gate transistor which includes a second conductive type transistor, the additional power gate transistor receiving an inverted second signal at a gate electrode thereof.

14. A method comprising:

supplying a power supply voltage to an internal circuit when a power supply control signal is in active;

maintaining the supply of the power supply voltage to the internal circuit when an inactive state of the power supply control signal does not continue for a certain period; and

stopping the supply of the power supply voltage to the internal circuit when the inactive state of the power supply control signal continues for the certain period.

15. The method according to claim 14 , wherein

when the power supply control signal transitions to an active state after the inactive state of the power supply control signal has maintained for the certain period of time or more followed by stopping the supply of the power supply to the internal circuit, the supply of the power supply to the internal circuit is resumed.

16. The method according to claim 14 , wherein

the internal circuit includes a first circuit and a second circuit to both of which a first power supply and a second power supply are supplied when the power supply control signal is active; and

when the inactive state of the power supply control signal continues for the certain period of time or more, supply of the second power supply to the first circuit is stopped and supply of the first power supply to the first circuit is maintained, thereby maintaining an output node of the first circuit to have a same voltage as the first power supply, and supply of the first power supply to the second circuit is stopped and supply of the second power supply to the second circuit is maintained, thereby maintaining an output node of the second circuit to have a same voltage as the second power supply.

17. The method e according to claim 14 , wherein

the internal circuit includes a plurality of internal circuits, and when the power supply control signal transitions from the inactive state to the active state and the supply of the power supply to the internal circuits is resumed after the inactive state of the power supply control signal has maintained for the certain period of time or more and the supply of the power supply to the internal circuits has been then stopped, the supply of the power supply is resumed, being time shifted with respect to the internal circuits, respectively.