On-chip security method and apparatus
A boot method an apparatus are described which reduce the likelihood of a security breach in a mobile device, preferably in a situation where a reset has been initiated. A predetermined security value, or password, is stored, for example in BootROM. A value of a security location within FLASH memory is read and the two values are compared. Polling of the serial port is selectively performed, depending on the result of such comparison. In a presently preferred embodiment, if the value in the security location matches the predetermined security value, then polling of the serial port is not performed. This reduces potential security breaches caused in conventional arrangements where code may be downloaded from the serial port and executed, which allows anyone to access and upload programs and data in the FLASH memory, including confidential and proprietary information.
1. A boot method for use in a mobile device having flash memory storing boot instructions and having a serial port, the method comprising the steps of:
reading contents of a security location in the flash memory;
comparing the contents of the security location to a predetermined security value;
on a first result of comparing the contents of the security location to the predetermined security value, polling the serial port for activity based on the result of the comparison; and
on a second result of comparing the contents of the security location to the predetermined security value, jumping to a boot location in the flash memory to execute instructions stored therein.
2. A boot method according to claim 1 wherein the first result comprises the contents of the security location not matching the predetermined security value.
3. A boot method according to claim 2 wherein the second result comprises the contents of the security location matching the predetermined security value.
4. A boot method according to claim 1 further comprising the step of downloading code into internal SRAM located in the mobile device in response to a detection of serial port activity.
5. A boot method according to claim 4 further comprising the step of executing an instruction in the downloaded code.
6. A boot method according to claim 1 wherein the predetermined security value is stored in a BootROM located in the mobile device.
7. A boot method according to claim 1 wherein the step of reading is performed in response to a reset command.
8. An apparatus for use in a mobile device having a serial port, the apparatus comprising:
a first memory device having a predetermined security value stored therein;
a second memory device having a security location; and
a processor in communication with the first memory device and second memory device, the processor being configured to:
compare the contents of the security location to the predetermined security value;
on a first result of comparing the contents of the security location to the predetermined security value, polling the serial port for activity based on the result of the comparison; and
on a second result of comparing the contents of the security location to the predetermined security value, in to a boot location in the flash memory to execute instructions stored therein.
9. An apparatus according to claim 8 wherein the first memory device comprises a Boot Read Only Memory (BootROM).
10. An apparatus according to claim 8 wherein the second memory device comprises a flash memory.
11. An apparatus according to claim 8 further comprising a reset circuit in communication with the processor for initiating a reset process.
12. An apparatus according to claim 8 wherein the processor compares contents of the security location and said predetermined security value in response to initiation of a reset process.
13. An apparatus according to claim 8 wherein the first memory device is located on an ASIC.
14. An apparatus according to claim 8 wherein the processor is located on an ASIC.
15. An apparatus according to claim 8 wherein the processor comprises a microcontrol unit connected to the serial port.
16. An apparatus according to claim 8 wherein the processor comprises a digital signal processor connected to the second memory device.