Encoding data based on weight constraints

1. A method for encoding data to be placed into a weight constrained memory array performed by a physical computing system, the method comprising:

designating a set of crosspoints within a crossbar memory array as indicator crosspoints and a set of crosspoints within said memory array as data crosspoints, said set of indicator crosspoints selected so that a net number of times that each data crosspoint has been flipped can be determined from a subset of said set of indicator crosspoints;

placing an input stream of data into a matrix corresponding to crosspoints within said memory array, bits of said input stream being placed into matrix elements that correspond to data crosspoints of said memory array;

setting each matrix element corresponding to indicator crosspoints to a value corresponding to a fixed resistive state; and

flipping each bit corresponding to a conductor of said memory array until no conductors within said memory array violate a weight constraint.

2. The method of claim 1 , further comprising, writing said bits of said matrix into their corresponding crosspoints of said crossbar memory array.

3. The method of claim 2 , further comprising decoding said array by:

copying data stored within said array into a decoding matrix, each element of said decoding matrix corresponding to a crosspoint within said memory array;

for each element within said decoding matrix corresponding to a data crosspoint, flipping that bit if a state of said subset of said set of indicator crosspoints indicates that that bit has been flipped an odd number of times; and

forming an output stream of data from the decoding matrix elements corresponding to the data crosspoints within said memory array.

4. The method of claim 1 , wherein said set of indicator crosspoints is determined by:

forming a binary structure matrix wherein each row corresponds to each conductor within said crossbar memory array and each column corresponds to each crosspoint within said crossbar memory array;

for each row of said structure matrix, storing a ‘1’ in each column that corresponds to a crosspoint that is along a conductor corresponding to that row and otherwise storing a ‘0’; and

determining a set of basis columns for said structure matrix, crosspoints associated with said basis columns being assigned as indicator crosspoints.

5. The method of claim 1 , wherein a programmable memory element at each of said crosspoints is a resistive memory element.

6. The method of claim 1 , wherein said crossbar array is a disjointed crossbar memory array.

7. The method of claim 1 , wherein said weight constraint comprises a rule that no more than half of the crosspoints along a single conductor should be in a low resistive state.

8. A computing system comprising:

at least one processor;

a crossbar memory array; and

a memory communicatively coupled to the at least one processor, the memory comprising computer executable code that, when executed by the at least one processor, causes the at least one processor to:

designate a set of crosspoints within said crossbar memory array as indicator crosspoints and a set of crosspoints within said memory array as data crosspoints, said set of indicator crosspoints selected so that a net number of times that each data crosspoint has been flipped can be determined from a subset of said set of indicator crosspoints;

place an input stream of data into a matrix corresponding to crosspoints within said memory array, bits of said input stream being placed into matrix elements that correspond to data crosspoints of said memory array;

set each matrix element corresponding to indicator crosspoints to a value corresponding to a fixed resistive state; and

flip each bit corresponding to a conductor of said memory array until no conductors within said memory array violate a weight constraint.

9. The system of claim 8 , wherein said at least one processor is further configured to write said bits of said matrix into their corresponding crosspoints of said crossbar memory array.

10. The system of claim 9 , wherein to decode said memory array, said at least one processor is further configured to:

copy data stored within said array into a decoding matrix, each element of said decoding matrix corresponding to a crosspoint within said memory array;

for each element within said decoding matrix corresponding to a data crosspoint, flip that bit if a state of said subset of said set of indicator crosspoints indicates that that bit has been flipped an odd number of times; and

form an output stream of data from the decoding matrix elements corresponding to the data crosspoints within said memory array.

11. The system of claim 8 , wherein, to determine said set of indicator crosspoints, said at least one processor is further configured to:

form a binary structure matrix wherein each row corresponds to each conductor within said crossbar memory array and each column corresponds to each crosspoint within said crossbar memory array;

for each row of said structure matrix, storing a ‘1’ in each column that corresponds to a crosspoint that is along a conductor corresponding to that row and otherwise storing a ‘0’; and

determine a set of basis columns for said structure matrix, crosspoints associated with said basis columns being assigned as indicator crosspoints.

12. The system of claim 8 , wherein a programmable memory element at each of said crosspoints is a resistive memory element.

13. The system of claim 8 , wherein said crossbar array is a disjointed crossbar memory array.

14. The system of claim 8 , wherein said weight constraint comprises a rule that no more than half of the crosspoints along a single conductor should be in a low resistive state.

15. A method for encoding data to be placed into a weight constrained memory array performed by a physical computing system, the method comprising:

placing an input stream of data into a matrix corresponding to crosspoints within a crossbar memory array, bits of said input stream being placed into matrix elements that have been designated as data crosspoints;

setting each matrix element that corresponds to a set of crosspoints within said memory array that have been designated as indicator crosspoints to a value corresponding to a fixed resistive state, said set of indicator crosspoints being designated so that a net number of times a bit stored in each of said data crosspoints can be identified by a state of a subset of said set of indicator crosspoints; and

examining each conductor of said memory array and flipping each bit corresponding to a crosspoint of that conductor if more than half of the crosspoints on that conductor are in a low resistive state.