METHODS OF MONITORING OPERATION OF PROGRAMMABLE LOGIC
Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.
1 . A method of monitoring operation of programmable logic for a streaming processor, the method comprising:
generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph;
inserting, on each edge of the graph, monitoring hardware to monitor flow of data along the edge.
2 . The method according to claim 1 , in which each edge comprises flow control signals and a data bus for flow of data, and wherein the method comprises coupling the monitoring hardware to both the flow control signals and the data bus.
3 . The method according to claim 1 , comprising reading parameters associated with the data with the monitoring hardware, the parameters including the number of valid data cycles.
4 . The method according to claim 1 , comprising performing a checksum on passing data with the monitoring hardware.
5 . The method according to claim 4 , comprising performing a checksum on at least two consecutive edges and comparing the checksum values.
6 . The method according to claim 1 , comprising determining the number of valid cycles along every edge in the graph thereby identifying one or more routes taken by data through the graph.
7 . The method according to claim 1 , comprising determining the number of valid cycles along at least two consecutive edges and comparing the numbers.
8 . The method according to claim 1 , in which at least one of the nodes comprises a FIFO memory.
9 . A method of monitoring operation of programmable logic for a streaming processor, the method comprising:
generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph;
inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data, for onward transmission to a connected node.
10 . A method according to claim 9 , in which the data-generating hardware is provided on each edge in the graph.
11 . A method according to claim 9 or 10 , the data-generating hardware is arranged to generate a count signal.
12 . A method according to any of claims 9 to 11 , in which each edge comprises a data bus for flow of data and flow control signals for the transmission of flow control signals, and wherein the method comprises coupling the data-generating hardware to both the flow control signals and the data bus.
13 . A method according to claim 12 when dependent on claim 11 , comprising incrementing the counter when the flow control signals indicate that data should transfer between the nodes.
14 . A method according to claim 12 or 13 , in which the data-generating hardware is arranged to receive an input from the data bus and to provide as an output a count signal having the same flow control pattern as the data received on the data bus.
15 . A method according to any of claims 9 to 14 , comprising coupling the control signals to a data generator within the count-generating hardware, and in dependence on the flow control signals generating the count signal.
16 . A method according to any of claims 9 to 14 , comprising operating the data-generating hardware at the same clock rate as the data received from the upstream node.
17 . A streaming processor comprising:
plural nodes for processing streaming data;
at least one edge connecting the one or more nodes;
monitoring hardware provided on each of the edges to monitor flow of data along the respective edge.
18 . A streaming processor comprising:
plural nodes for processing streaming data;
at least one edge connecting each pair of the one or more nodes;
data-generating hardware arranged to receive data from an upstream node in a pair of nodes and generate data at known values having the same flow control pattern as the received data for onward transmission to a downstream node in the pair of nodes.
19 . A streaming processor according to claim 18 , in which the data-generating hardware comprises a data generator arranged to generate a count signal.
20 . A streaming processor according to any of claims 17 to 19 , in which the streaming processor is provided on an FPGA.
21 . A tool for enabling the monitoring of operation of programmable logic for a streaming processor, the tool comprising:
a graph generator for generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph;
a monitoring hardware generator, for generating monitoring hardware on each edge of the graph, the monitoring hardware being configured to monitor flow of data along the edge.
22 . A tool for enabling the monitoring of operation of programmable logic for a streaming processor, the tool comprising:
a graph generator for generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph;
a hardware generator for generating and inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data, for onward transmission to a connected node.
23 . A method of monitoring operation of programmable logic for a streaming processor, the method comprising:
generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes, the edges including control signals and a data bus;
inserting, on at least one edge monitoring hardware coupled to both the control signals and the data bus.