SOI wafer, method for producing same, and method for manufacturing semiconductor device
View Patent ↗An SOI wafer including: a supporting substrate 1 ; a BOX layer 2 provided above the supporting substrate 1 , the BOX layer 2 being formed by a thermal oxidization; a gettering layer 3 provided immediately on the BOX layer 2 and mainly composed of a silicon which contains one or more of oxygen, carbon and nitrogen and contains at least oxygen; and an S layer 4 in which semiconductor devices are to be formed, the S layer 4 being mainly composed of a monocrystalline silicon.
1. An SOI wafer comprising:
a supporting substrate mainly composed of a monocrystalline silicon;
an insulation layer being a silicon oxide layer provided on a surface of the supporting substrate;
a gettering layer provided immediately on the insulation layer and mainly composed of a silicon which contains two or more of oxygen, carbon and nitrogen and contains at least oxygen and nitrogen; and
a monocrystalline silicon layer provided immediately on the gettering layer.
2. The SOI wafer of claim 1 , wherein
the gettering layer contains germanium or an electrically conductive impurity.
3. The SOI wafer of claim 1 , wherein
a state of the silicon constituting the gettering layer is one of monocrystalline, polycrystalline, noncrystalline, and a mixture of noncrystalline and polycrystalline.
4. The SOI wafer of claim 3 , wherein
the state of the silicon constituting the gettering layer is one of noncrystalline and a mixture of noncrystalline and polycrystalline.
5. The SOI wafer of claim 1 , wherein
a concentration of the oxygen contained in the gettering layer is 1×10 18 atoms/cm 3 or more.
6. The SOI wafer of claim 1 , wherein
the gettering layer contains carbon, and a concentration of the carbon contained in the gettering layer is 3×10 16 atoms/cm 3 or more.
7. The SOI wafer of claim 1 , wherein
a concentration of the nitrogen contained in the gettering layer is 1×10 14 atoms/cm 3 or more.
8. The SOI wafer of claim 1 , wherein
a thickness of the monocrystalline silicon layer is in a range from 1 μm to 50 μm.
9. The SOI wafer of claim 1 , wherein
a thickness of the gettering layer is smaller than a thickness of the monocrystalline silicon layer.
10. The SOI wafer of claim 1 , wherein
the SOI wafer is used as a material for manufacturing a high-voltage device of 200 V or more, or as a material for manufacturing an image device having a buried photodiode, and
a thickness of the monocrystalline silicon layer is in a range from 1 μm to 10 μm.
11. The SOI wafer of claim 1 , wherein
the SOI wafer is used as a material for manufacturing a high-voltage device of 500 V or more, and
a thickness of the monocrystalline silicon layer is in a range from 10 μm to 50 μm.