Parallel packet processor with session active checker

1. An apparatus for processing received packets, comprising:

a plurality of packet processors

a session memory coupled to and shared by the plurality of packet processors, the session memory to store session configuration and session statistics information for a plurality of communication sessions

a session active memory separate from the session memory, the session active memory to store one or more session identifiers corresponding to packets currently being processed by the plurality of packet processors

a comparator that compares a session identifier extracted from a received packet with the one or more session identifiers stored in the session active memory to determine if another packet belonging to the same communication session as the received packet is currently being processed

packet forwarding logic to select one of the plurality of processors to process the received packet, the packet forwarding logic configured to, in the case that the comparator determines that another packet belonging to the same communication session as the received packet is currently being processed, wait until the processing of the another packet is complete before sending the received packet to the selected packet processor.

2. The apparatus of claim 1 , further comprising:

an input buffer adapted to store a plurality of received packets

wherein, in the case that the session active checker determines that another packet belonging to same communication session as the received packet is currently being processed, the session active checker temporarily stores the received packet and retrieves another received packet from the input buffer.

3. The apparatus of claim 1 , wherein the packet forwarding logic is further configured to, in the case that the session active checker determines that no other packet belonging to the same communication session as the received packet is currently being processed, send the received packet to the selected one of the plurality of packet processors.

4. The apparatus of claim 1 , wherein the packet forwarding logic is configured to balance a load on the plurality of packet processors.

5. The apparatus of claim 4 , further comprising:

a plurality of first-in first-out (FIFO) queues, each of the plurality of FIFO queues coupled between the forwarding logic and a respective one the of the plurality of packet processors to store packets sent from the forwarding logic to the respective packet processor.

6. The apparatus of claim 5 , wherein the packet forwarding logic is configured to select the packet processor to process the received packet based, at least in part, on a number of available slots in each of the plurality of FIFO queues.

7. A method for processing received packets, comprising:

storing session configuration and session statistics information for a plurality of communication sessions in a session memory coupled to and shared by the plurality of packet processors

storing one or more session identifiers corresponding to packets currently being processed by a plurality of packet processors in a session active memory separate from the session memory

comparing a session identifier extracted from a received packet with the one or more session identifiers stored in the session active memory to determine if another packet belonging to the same communication session as the received packet is currently being processed

selecting a packet processor of the plurality of processors to process the received packet

sending the received packet to the selected packet processor

waiting, in the case that the comparing determines that another packet belonging to the same communication session as the received packet is currently being processed, until the processing of the another packet is complete before sending the received packet to the selected packet processor.

8. The method of claim 7 , further comprising:

storing a plurality of received packets in an input buffer

in the case that the session active checker determines that another packet belonging to same communication session as the received packet is currently being processed, temporarily storing the received packet and retrieving another received packet from the input buffer.

9. The method of claim 7 , wherein selecting a packet processor to process the received packet is performed in accordance with rules to balance a load on the plurality of packet processors.

10. The method of claim 9 , further comprising:

storing packets sent to the plurality of packet processor in a plurality of first-in first-out (FIFO) queues, each of the plurality of FIFO queues for storing packets for a respective one the of the plurality of packet processors.

11. The method of claim 10 , wherein selecting a packet processor to process the received packet is based, at least in part, on a number of available slots in each of the plurality of FIFO queues.

12. A non-transitory computer readable storage medium having programming code stored thereon which, when used to program a field programmable gate array, will cause the field programmable gate array (FPGA) to be configured as an apparatus for processing received packets, the apparatus comprising:

a plurality of packet processors

a memory controller coupled to the plurality of processors, the memory controller providing an interface to a session memory external to the FPGA, the session memory shared by the plurality of packet processors to store session configuration and session statistics information for a plurality of communication sessions

a session active memory separate from the session memory, the session active memory to store one or more session identifiers corresponding to packets currently being processed by the plurality of packet processors

a comparator that compares a session identifier extracted from a received packet with the one or more session identifiers stored in the session active memory to determine if another packet belonging to the same communication session as the received packet is currently being processed

packet forwarding logic to select one of the plurality of processors to process the received packet, the packet forwarding logic configured to, in the case that the comparator determines that another packet belonging to the same communication session as the received packet is currently being processed, wait until the processing of the another packet is complete before sending the received packet to the selected packet processor.

13. The non-transitory computer readable storage medium of claim 12 , the apparatus further comprising:

an input buffer adapted to store a plurality of received packets

wherein, in the case that the session active checker determines that another packet belonging to same communication session as the received packet is currently being processed, the session active checker temporarily stores the received packet and retrieves another received packet from the input buffer.

14. The non-transitory computer readable storage medium of claim 12 , wherein the packet forwarding logic is further configured to, in the case that the session active checker determines that no other packet belonging to the same communication session as the received packet is currently being processed, send the received packet to the selected one of the plurality of packet processors.

15. The non-transitory computer readable storage medium of claim 12 , wherein the packet forwarding logic is configured to balance a load on the plurality of packet processors.

16. The non-transitory computer readable storage medium of claim 15 , the apparatus further comprising:

a plurality of first-in first-out (FIFO) queues, each of the plurality of FIFO queues coupled between the forwarding logic and a respective one the of the plurality of packet processors to store packets sent from the forwarding logic to the respective packet processor.

17. The non-transitory computer readable storage medium of claim 16 , wherein the packet forwarding logic is configured to select the packet processor to process the received packet based, at least in part, on a number of available slots in each of the plurality of FIFO queues.