Method for offset compensation of a switched-capacitor amplifier and switched capacitor amplifier arrangement

1. A method for offset compensation of a switched-capacitor amplifier comprising:

in a reset phase, feeding an output voltage of the amplifier according to a damped feedback loop gain to a first amplifier input as a function of an offset voltage; and

in at least one working phase, compensating an offset of the amplifier as a function of the offset voltage by superimposing the output voltage on an input voltage of the amplifier according to a feedback loop gain,

wherein the damped feedback loop gain is adjusted as a function of a quotient of resistance values using a voltage divider.

2. The method according to claim 1 , wherein the damped feedback loop gain is adjusted in the reset phase by damping the feedback loop gain.

3. The method according to claim 1 , wherein the frequency of at least one pole of a transfer function of the amplifier is shifted by means of the damped feedback loop gain.

4. The method according to claim 1 , wherein the damped feedback loop gain is adjusted by changing over between a first and a second feedback loop.

5. A method for offset compensation of a switched-capacitor amplifier comprising:

in a reset phase, feeding an output voltage of the amplifier according to a damped feedback loop gain to a first amplifier input as a function of an offset voltage; and

in at least one working phase, compensating an offset of the amplifier as a function of the offset voltage by superimposing the output voltage on an input voltage of the amplifier according to a feedback loop gain,

wherein the offset voltage is buffered in the reset phase by a charge storage means and is connected in the at least one working phase to the input voltage for offset compensation, and

wherein the feedback loop gain is adjusted as a function of a quotient of capacitance values of the charge storage means.

6. The method according to claim 1 , wherein the reset phase and the at least one working phase follow one another alternately in time.

7. A switched-capacitor amplifier arrangement with an input and an output, comprising:

an amplifier, having a first amplifier input coupled by an offset compensation device to the input, and a second amplifier input adapted to be supplied with an offset voltage, wherein the amplifier comprises an amplifier output that is connected to the output; and

a feedback loop wherein the amplifier output is either electrically coupled to the offset compensation device by first switches via a damping member in a reset phase, or directly by second switches in at least one working phase,

wherein the input is likewise electrically coupled by the second switches to the offset compensation device in the at least one working phase, and

wherein the damping member comprises a voltage divider that is coupled by at least two of the first switches to the amplifier output and to the offset compensation device, and is configured to adjust a loop gain of the feedback loop.

8. The amplifier arrangement according to claim 7 , wherein the voltage divider comprises a first and second resistor, and wherein a quotient of resistance values of the first and second resistors is proportional to the feedback loop gain.

9. A switched-capacitor amplifier arrangement with an input and an output, comprising:

an amplifier, having a first amplifier input coupled by an offset compensation device to the input, and a second amplifier input adapted to be supplied with an offset voltage, wherein the amplifier comprises an amplifier output that is connected to the output; and

a feedback loop wherein the amplifier output is either electrically coupled to the offset compensation device by first switches via a damping member in a reset phase, or directly by second switches in at least one working phase,

wherein the input is likewise electrically coupled by the second switches to the offset compensation device in the at least one working phase,

wherein the offset compensation device comprises a charge storage means, and

wherein the charge storage means comprises a first and a second capacitor coupled to one another, whose facing electrodes are connected to the first amplifier input and whose electrodes facing away from one another are connected by the first switches to a reference potential.

10. The amplifier arrangement according to claim 7 , wherein the amplifier comprises an operational amplifier.

11. The amplifier arrangement according to claim 7 , wherein at least one of the first switches or the second switches comprises one or more transistors.