Securing a storage element for a binary datum, control register and chip card
Securing a storage element for a binary datum, control register and chip card. This element ( 60 ) for storing a binary datum (D) inputs a signal representative of said binary datum, said storage to be carried out when an enable signal (ENA) is at a first predetermined level, supplies an output signal (Q) the state whereof represents the datum stored in said storage element ( 10 ), and detects an attack aimed at said enable signal (ENA) or at a signal internal to said storage element.
1. A device of storage element configured to store a single binary datum, the storage element comprising:
a flip-flop formed by a plurality of logic gates, the flip-flop being configured to store the single binary datum;
means for inputting an enable signal to the flip-flop;
means for generating a secure enable signal;
means for inputting a signal representative of said binary datum to the flip-flop, said storage to be performed by the flip-flop when the enable signal is at a first predetermined level;
means for supplying an output signal from the storage element, the state of the output signal representing whereof represents the datum stored in said flip-flop;
means for detecting commutation of the output signal; and
means for detecting an attack directly against said enable signal or an intermediate signal internal to said storage element so as to prevent the storage of a datum in the storage element upon detecting attack.
2. The storage element according to claim 1 , comprising a terminal configured to receive said enable signal, and comprising upstream of said terminal:
means for generating a secure enable signal different from said enable signal in that it takes on a second level that is different from said first level in the event of detection of an attack aimed at said enable signal; and
means for supplying said secure enable signal as input to said terminal.
3. The storage element according to claim 2 , wherein said means of generation comprise a gate configured to invert a complementary signal of said enable signal and a logic function configured to produce said secure enable signal by performing a logical AND between said enable signal and said inverted signal.
4. The storage element according to claim 2 , comprising means for generating a pulse if said secure enable signal is at said second level at a time that said commutation is detected.
5. The storage element according to claim 4 , comprising means for extending the duration of said pulse.
6. The storage element according to claim 1 , comprising:
means for detecting commutation of said output signal; and
means for detecting an attack if said enable signal is not at said first level at a time of detecting of said commutation.
7. The storage element according to claim 6 , comprising means for generating a commutation signal, one level of the commutation signal representing a commutation of said output signal from at least one first output signal level to a second output signal level.
8. The storage element according to claim 7 , comprising a second output for a complementary signal of said output signal and wherein said means of generating the commutation signal comprise a first logic function configured to produce said commutation signal by performing a logical NOT AND between said output signal and its complementary signal.
9. The storage element according to claim 7 , wherein said means for generating the commutation signal comprise:
a pair of inverters configured to invert said output signal and its complementary signal, respectively; and
a second logic function configured to produce said commutation signal by performing a logical NOT AND between said inverted signals.
10. A control register comprising at least one storage element according to claim 1 .
11. A microcircuit card comprising at least one control register according to claim 10 .