IP Library Granted Patent US 8,383,516
Granted Patent B2
US 8,383,516 · App. 13/219,996 · Granted Feb 26, 2013

Semiconductor device and method for manufacturing the same

Inventors: Makoto Takahashi (Kawasaki, JP); Minoru Endou (Kawasaki, JP)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,383,516
App. No.
13/219,996
Granted
Feb 26, 2013
Kind
B2
Abstract

A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive pattern is formed over the isolation insulating film, and an insulating film is formed over the isolation insulating film, the conductive pattern and the side face of the conductive pattern, and the side face of the conductive pattern comprises a notch.

Claims (17)

1. A method for manufacturing a semiconductor device, the method comprising:

forming an isolation insulating film in a semiconductor substrate;

forming a conductive film over the isolation insulating film; and

forming a conductive pattern by patterning the conductive film through a first etching and a second etching following the first etching,

wherein the second etching is performed under conditions in which an amount of a deposition deposited over a side face of the conductive pattern is larger than in the first etching.

2. The method according to claim 1 , wherein the second etching is performed under conditions where the amount of the deposition deposited per unit time is larger than in the first etching.

3. The method according to claim 2 , wherein a silicon film is formed as the conductive film, wherein an etching gas including Cl 2 is used in the first etching and the second etching, wherein a flow rate of the Cl 2 is lower in the second etching than in the first etching.

4. The method according to claim 2 , wherein a silicon film is formed as the conductive film, wherein an etching gas including O 2 is used in the first etching and the second etching, wherein a flow rate of the O 2 is higher in the second etching than in the first etching.

5. The method according to claim 2 , wherein a silicon film is formed as the conductive film, wherein a substrate temperature is set to be lower in the second etching than in the first etching.

6. The method according to claim 2 , wherein a silicon film is formed as the conductive film, wherein a temperature of an inner wall of an etching chamber used in the second etching is set to be lower than in the first etching.

7. The method according to claim 3 , wherein an etching gas used in the first etching and the second etching includes at least one of Cl 2 , O 2 and HBr.

8. The method according to claim 3 , wherein the first etching and the second etching are performed by reactive ion etching.

9. The method according to claim 1 , wherein a notch is formed in the side face of the conductive pattern through the second etching.

10. The method according to claim 9 , wherein a depth of the notch is controlled in accordance with etching time of the second etching or a flow rate of O 2 included in an etching gas used in the second etching.

11. The method according to claim 1 , wherein the second etching is performed under conditions in which etch selectivity between the isolation insulating film and the conductive film is higher than in the first etching.

12. The method according to claim 11 , wherein a silicon oxide film is formed as the isolation insulating film and a silicon film is formed as the conductive film, wherein an etching gas used in the first etching and the second etching includes Cl 2 and O 2 , and the second etching is performed under conditions in which a flow rate of the O 2 is higher than in the first etching.

13. The method according to claim 1 , wherein an insulating film is formed over the isolation insulating film, the conductive pattern and the side face of the conductive pattern, wherein a control gate conductive film is formed on the insulating film, wherein a control gate is formed by patterning the control gate conductive film, wherein the insulating film is patterned allowing for a portion of the insulating film to remain below the control gate, wherein the conductive pattern is patterned allowing for a portion of the conductive pattern to remain as a floating gate below the control gate.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded Jun 12, 2024
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 067699/0527 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
Priority Claims (1)
JP 2008-63389 · Mar 12, 2008 · national
Continuity (2)
Division 12401382 · Mar 10, 2009
Related Publication 20110312154A1 · Dec 22, 2011