Thin film transistor and flat panel display device including the same
View Patent ↗A thin film transistor (TFT) and a flat panel display device including the same. The TFT includes a substrate, a gate electrode formed over the substrate, the gate electrode formed with silicon doped with impurities, a gate wiring connected to the gate electrode, an active layer formed over the gate electrode, and source and drain electrodes connected to the active layer. According to such a structure, since heat flow to the gate electrode during crystallization of the active layer may be prevented, stable crystallization of the active layer may be performed, and thus an error rate of a product may be decreased.
1. A TFT comprising:
a substrate;
a gate electrode formed over the substrate, the gate electrode formed with silicon doped with impurities;
a gate wiring comprising a metal layer formed over at least portions of the gate electrode;
an active layer formed over the gate electrode; and
source and drain electrodes connected to the active layer,
wherein the gate wiring comprises:
a silicon layer doped with the same impurities as the silicon forming the gate electrode, and on the same layer as the gate electrode, and
a metal layer formed over the silicon layer.
2. The TFT of claim 1 , wherein the active layer is formed of amorphous silicon crystallized by heating.
3. The TFT of claim 1 , wherein the impurities are N-type impurities.
4. The TFT of claim 1 , further comprising an etching stop layer on the active layer configured to protect the active layer from being etched.
5. The TFT of claim 1 , wherein a gate insulating layer is formed between the gate electrode and the active layer.
6. The TFT of claim 1 , wherein a passivation layer is formed over the source and drain electrodes.
7. A flat panel display device including a TFT and a pixel unit driven by the TFT, wherein the TFT comprises:
a substrate,
a gate electrode formed over the substrate and formed of silicon doped with impurities,
a gate wiring comprising a metal layer formed over at least portions of the gate electrode,
an active layer formed over the gate electrode, and
source and drain electrodes connected to the active layer,
wherein the gate wiring comprises:
a silicon layer doped with the same impurities as the silicon forming the gate electrode, and on the same layer as the gate electrode, and
a metal layer formed over the silicon layer.
8. The flat panel display device of claim 7 , wherein the active layer is formed of amorphous silicon crystallized by heating.
9. The flat panel display device of claim 7 , wherein the impurities are N-type impurities.
10. The flat panel display device of claim 7 , further comprising an etching stop layer on the active layer configured to protect the active layer from being etched.
11. The flat panel display device of claim 7 , wherein a gate insulating layer is formed between the gate electrode and the active layer.
12. The flat panel display device of claim 7 , wherein a passivation layer is formed over the source and drain electrodes.
13. The flat panel display device of claim 7 , wherein the pixel unit comprises a pixel electrode connected to the source or drain electrode, an opposite electrode facing the pixel electrode, and an emission operating layer interposed between the pixel electrode and the opposite electrode configured to operate according to a voltage applied between the pixel electrode and the opposite electrode.
14. The flat panel display device of claim 13 , wherein the emission operating layer comprises at least one of an organic emission layer and a liquid crystal layer.