Memory element and memory device
View Patent ↗There are provided a memory element and a memory device in which the state of erasing remains stable by deactivation of a localized site(s) formed inside of a resistance change layer. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer including an n-type dopant or a p-type dopant, and disposed on the first electrode side, and an ion source layer disposed between the resistance change layer and the second electrode.
1. A memory element, comprising:
a first electrode, a memory layer, and a second electrode in this order,
wherein,
the memory layer includes:
(a) a resistance change layer including (i) tellurium, sulfur, or selenium, and (ii) an n-type dopant or a p-type dopant, the resistance change layer being disposed on the first electrode, and
(b) an ion source layer in contact with the resistance change layer, the ion source layer having mobile ions that diffuse into the resistance change layer when a first voltage is applied, and
the n-type or the p-type dopant of the resistance change layer has a concentration that is approximately equal to an amount of mobile ions that remains in the resistance change layer after the mobile ions move from the resistance change layer to the ion source layer when a second voltage is applied, the n-type or the p-type dopant and its concentration being effective to deactivate localized sites that occur in the resistance change layer.
2. The memory element according to claim 1 , wherein the concentration of the n-type dopant or the p-type dopant is 10 16 cm −3 or higher but 10 20 cm −3 or lower.
3. The memory element according to claim 1 , wherein the resistance change layer exhibits a localized level distribution in an energy band gap like a p-type semiconductor, and includes the n-type dopant.
4. The memory element according to claim 1 , wherein the resistance change layer exhibits a localized level distribution in an energy band gap on a lower-energy side from a center of a forbidden band.
5. The memory element according to claim 1 , wherein the n-type dopant is a tetravalent impurity element for substitution of cations.
6. The memory element according to claim 5 , wherein the tetravalent impurity element is one or more of carbon (C), silicon (Si), germanium (Ge), tin (Sn), titanium (Ti), zirconium (Zr), and hafnium (Hf).
7. The memory element according to claim 1 , wherein the resistance change layer shows a localized level distribution in an energy band gap like an n-type semiconductor, and includes the p-type dopant.
8. The memory element according to claim 1 , wherein the resistance change layer shows a localized level distribution in an energy band gap on a higher-energy side from a center of a forbidden band.
9. The memory element according to claim 1 , wherein the p-type dopant is a divalent impurity element for substitution of cations, or a pentavalent impurity element for substitution of anions.
10. The memory element according to claim 9 , wherein the divalent impurity element is one or more of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), and cadmium (Cd).
11. The memory element according to claim 9 , wherein the pentabalent impurity element is one or more of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), vanadium (V), niobium (Nb), and tantalum (Ta).
12. The memory element according to claim 1 , wherein the resistance change layer includes a metallic element that serves as a trivalent cation.
13. The memory element according to claim 1 , wherein when one of the first and second voltages is applied, a low-resistance section is formed by migration of mobile ions, and the resistance change layer shows a change of resistance.
14. A memory device, comprising:
a plurality of memory elements, each memory element including a first electrode, a memory layer, and a second electrode in this order; and
a pulse application section applying a voltage or current pulse selectively to the plurality of memory elements,
wherein,
the memory layer of each memory element includes:
(a) a resistance change layer including (i) tellurium, sulfur, or selenium, and (ii) an n-type dopant or a p-type dopant, the resistance change layer being provided on the first electrode, and
(b) an ion source layer in contact with the resistance change layer, the ion source layer having mobile ions that diffuse into the resistance change layer when a first voltage is applied, and
the n-type or the p-type dopant of the resistance change layer has a concentration that is approximately equal to an amount of mobile ions that remains in the resistance change layer after the mobile ions move from the resistance change layer to the ion source layer when a second voltage is applied, the n-type or the p-type dopant and its concentration being effective to deactivate localized sites that occur in the resistance change layer.
15. The memory device according to claim 14 , wherein the resistance change layer exhibits a localized level distribution in an energy band gap like a p-type semiconductor, and includes the n-type dopant.
16. The memory device according to claim 14 , wherein the resistance change layer shows a localized level distribution in an energy band gap like an n-type semiconductor, and includes the p-type dopant.