Data mask encoding in data bit inversion scheme
View Patent ↗Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte.
1. A system comprising an encoding circuit, the encoding circuit comprising:
a flip-flop configured to output a first data;
a comparator configured to compare the first data with an input data to output a comparison result;
a first XOR gate configured to receive the input data and the comparison result and output a second data;
a second XOR gate configured to receive the first data and a mask pattern and output a third data;
an OR gate configured to receive a mask information and the comparison result and output a control signal; and
a multiplexer configured to selectively output one of the second data and the third data as a fourth data, based on the mask information,
wherein the flip-flop latches the fourth data.
2. The system as claimed in claim 1 ,
wherein the comparison result is produced based on a number of transitions between the input data and the first data.
3. The system as claimed in claim 2 ,
wherein the mask pattern comprises a plurality of bits, and a value “1” is commonly set into some bits among the plurality of bits, and
wherein a number of the some bits is equal to or larger than a predetermined number.
4. The system as claimed in claim 3 ,
wherein the predetermined number is four when the plurality of bits is eight bits.
5. The system as claimed in claim 1 comprising a decoding circuit, the decoding circuit comprising:
a second flip-flop configured to latch the fourth data and output a fifth data;
a third XOR gate configured to receive the fourth data and the control signal;
a fourth XOR gate configured to receive the fourth data and the fifth data and output a sixth data;
a second comparator configured to compare the sixth data with the mask pattern to output a second comparison result; and
a logic gate configured to receive the control signal and the second comparison result.
6. The system as claimed in claim 5 ,
wherein the second comparator comprises a plurality of XOR gates each receiving a corresponding one of bits constituting the sixth data and a corresponding one of bits constituting the mask pattern.
7. The system as claimed in claim 1 comprising a decoding circuit, the decoding circuit comprising:
a second flip-flop configured to latch the fourth data and output a fifth data;
a third XOR gate configured to receive the fourth data and the control signal;
a fourth XOR gate configured to receive the fourth data and the fifth data and output a sixth data;
a second comparator configured to receive the sixth data and generate a value based on bits of the six data; and
a logic gate configured to receive the control signal and the value.
8. The system as claimed in claim 7 ,
wherein the second comparator produces a first value when a number of bits indicating “1” among the bits of the six data is equal to or larger than a predetermined number, and produce a second value when the number of bits indicating “1” among the bits of the six data is smaller than the predetermined number.
9. The system as claimed in claim 8 ,
wherein the six data is eight bits and the predetermine number is four.