Semiconductor device having a bus configuration which reduces electromigration
View Patent ↗A semiconductor device includes: a first transistor; a second transistor; an interlayer insulating film covering the transistors; a rectangular-shaped first bus formed on the interlayer insulating film and connected to first source/drain regions; a rectangular-shaped second bus formed on the interlayer insulating film with spacing from the first bus and connected to third source/drain regions; an inter-bus interconnect formed between the first and second buses for connecting these buses; a first contact pad provided on the first bus, to which a wire is connected; and a second contact pad provided on the second bus, to which a wire is connected. The inter-bus interconnect is in contact with part of the side of the first bus facing the second bus and part of the side of the second bus facing the first bus. The first and second contact pads are respectively in contact with part of the first and second buses.
1. A semiconductor device, comprising:
a first transistor formed on a substrate, having first source/drain regions and second source/drain regions;
a second transistor formed on the substrate, having third source/drain regions and fourth source/drain regions;
an interlayer insulating film formed on the substrate to cover the first transistor and the second transistor;
a first bus in a rectangular shape in plan formed on the interlayer insulating film and connected to the first source/drain regions;
a second bus in a rectangular shape in plan formed on the interlayer insulating film with spacing from the first bus and connected to the third source/drain regions;
an inter-bus interconnect formed between the first bus and the second bus for connecting the first bus with the second bus;
a first contact pad provided on the first bus, to which a first wire is connected; and
a second contact pad provided on the second bus, to which a second wire is connected,
wherein the inter-bus interconnect is in contact with part of a side of the first bus facing the second bus and part of a side of the second bus facing the first bus,
the first contact pad is in contact with part of the first bus, and
the second contact pad is in contact with part of the second bus.
2. The semiconductor device of claim 1 , wherein both end portions of the side of the first bus facing the second bus and both end portions of the side of the second bus facing the first bus are not in contact with the inter-bus interconnect.
3. The semiconductor device of claim 1 , wherein
the inter-bus interconnect has a plurality of conductors for connecting the first bus with the second bus, and
the conductors are formed with spacing from each other.
4. The semiconductor device of claim 3 , wherein an opening separating the conductors from each other is provided on a straight line connecting the first contact pad and the second contact pad.
5. The semiconductor device of claim 1 , further comprising:
a third bus formed on the interlayer insulating film and connected to the second source/drain regions; and
a fourth bus formed on the interlayer insulating film and connected to the fourth source/drain regions,
wherein the third bus is formed on a side of the first bus opposite to the side thereof facing the second bus, and
the fourth bus is formed on a side of the second bus opposite to the side thereof facing the first bus.
6. The semiconductor device of claim 5 , wherein
the first bus and the third bus are formed right above a region of the substrate where the first transistor is formed, and
the second bus and the fourth bus are formed right above a region of the substrate where the second transistor is formed.
7. The semiconductor device of claim 5 , further comprising:
first lower source/drain lines, second lower source/drain lines, first upper source/drain lines, and second upper source/drain lines formed right above the first transistor; and
third lower source/drain lines, fourth lower source/drain lines, third upper source/drain lines, and fourth upper source/drain lines formed right above the second transistor,
wherein the first lower source/drain lines and the second lower source/drain lines are formed alternately in parallel with each other,
the third lower source/drain lines and the fourth lower source/drain lines are formed alternately in parallel with each other,
the first upper source/drain lines and the second upper source/drain lines are formed alternately in parallel with each other between the first and second lower source/drain lines and the first and third buses,
the third upper source/drain lines and the fourth upper source/drain lines are formed alternately in parallel with each other between the third and fourth lower source/drain lines and the second and fourth buses,
the first lower source/drain lines, the second lower source/drain lines, the third lower source/drain lines, and the fourth lower source/drain lines extend in a direction intersecting with the first upper source/drain lines, the second upper source/drain lines, the third upper source/drain lines, and the fourth upper source/drain lines,
the first lower source/drain lines, the second lower source/drain lines, the third lower source/drain lines, and the fourth lower source/drain lines are respectively connected to the first source/drain regions, the second source/drain regions, the third source/drain regions, and the fourth source/drain regions via contacts, and
the first upper source/drain lines, the second upper source/drain lines, the third upper source/drain lines, and the fourth upper source/drain lines are respectively connected to the first lower source/drain lines, the second lower source/drain lines, the third lower source/drain lines, and the fourth lower source/drain lines via first vias, and connected to the first bus, the third bus, the second bus, and the fourth bus via second vias.