IP Library Granted Patent US 8,686,499
Granted Patent B2
US 8,686,499 · App. 13/226,628 · Granted Apr 1, 2014

Semiconductor device

Inventors: Masaya Katayama (Yokohama, JP); Masayoshi Asano (Yokohama, JP)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,686,499
App. No.
13/226,628
Granted
Apr 1, 2014
Kind
B2
Abstract

A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.

Claims (36)

1. A semiconductor device comprising:

a semiconductor substrate of a first conduction type;

a first region of a second conduction type provided in the semiconductor substrate;

a second region of the first conduction type provided in the first region;

an isolation region provided over first region of a surface of the semiconductor substrate and the second region of a surface of the semiconductor substrate, and having a first opening and a second opening provided in a direction, the first opening provided at the first region, the second opening provided at a part of a junction of the first region and the second region of a surface of the semiconductor substrate, and an other part of the junction covered by the isolation region;

a gate electrode having a gate opening over the second region, provided over the isolation region and the second opening along the junction; and

a drain region and a source region of the second conduction type provided in the first region of the first opening and the second region of the second opening, respectively, with a part of the gate electrode therebetween.

2. The semiconductor device according to claim 1 , wherein:

the gate electrode includes an outer portion over the first region outside the junction and an inner portion over the second region inside the junction; and

first width of the outer portion of the part of the gate electrode between the drain region and the source region is narrower than or equal to second width of the outer portion of an other part of the gate electrode.

3. The semiconductor device according to claim 1 , wherein the drain region is provided away from the gate electrode in the first region of the first opening.

4. The semiconductor device according to claim 1 further comprising:

an insulating film provided over the semiconductor substrate so as to cover the gate electrode; and

a contact electrode provided in the insulating film and connected to a part of the gate electrode other than the part of the gate electrode between the drain region and the source region.

5. The semiconductor device according to claim 1 , wherein:

the isolation region has a third opening provided at the second region; and

a tap region of the first conduction type is provided in the third opening.

6. A semiconductor device comprising:

a semiconductor substrate of a first conduction type;

a first region of a second conduction type provided in the semiconductor substrate;

a second region of the first conduction type provided in the first region;

a gate electrode provided over a junction of first region of a surface of the semiconductor substrate and the second region of a surface of the semiconductor substrate along the junction; and

a drain region of the second conduction type provided in the first region;

a source region of the second conduction type provided in the second region and being surrounded by the gate electrode;

an isolation region provided over the first region and the second region, and having a first opening including the drain region and a second opening including the source region and the junction of the first region of the surface of the semiconductor substrate and the second region of the surface of the semiconductor substrate between the drain region and the source region; wherein

the gate electrode comprises a first part and a second part; and

the first part is provided between the drain region and the source region and the second part is not provided between the drain region and the source region.

7. The semiconductor device according to claim 6 , wherein:

the gate electrode includes an outer portion over the first region outside the junction and an inner portion over the second region inside the junction; and

first width of the outer portion of the first part of the gate electrode is narrower than or equal to second width of the outer portion of the second part of the gate electrode.

8. The semiconductor device according to claim 6 , wherein the drain region is provided away from the gate electrode in the first region.

9. The semiconductor device according to claim 6 , further comprising:

an insulating film provided over the semiconductor substrate so as to cover the gate electrode; and

a contact electrode provided in the insulating film and connected to the second part of the gate electrode.

10. The semiconductor device according to claim 6 , further comprising:

a tap region of the first conduction type in the second region inside the gate electrode.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2011
From: KATAYAMA, MASAYA; ASANO, MASAYOSHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 026882/0586 →
Priority Claims (1)
JP 2010-252479 · Nov 11, 2010 · national
Continuity (1)
Related Publication 20120119292A1 · May 17, 2012