Systems, methods and apparatus for local programming of quantum processor elements
View Patent ↗Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.
1. A quantum processor comprising:
a plurality of programmable devices including a plurality of qubits; and
a memory administration system including a plurality of communication conduits and a demultiplexer circuit, the memory administration system configured to couple to at least one of the programmable devices via at least one of the communication conduits.
2. The quantum processor of claim 1 wherein at least one programmable device and at least a portion of the memory administration system are formed by a material that is superconducting below a critical temperature.
3. The quantum processor of claim 1 wherein the programmable devices are selected from the group consisting of superconducting flux qubits, superconducting charge qubits, superconducting phase qubits, superconducting hybrid qubits, quantum dots, trapped ions, trapped neutral atoms, qubit couplers, superconducting qubit couplers, impurities, nuclear spin qubits, electronic spin qubits, and photonic qubits.
4. The quantum processor of claim 1 wherein the memory administration system comprises a plurality of components and at least one communication conduit is configured to communicably couple between at least one programmable device and at least one component of the memory administration system.
5. The quantum processor of claim 1 wherein the memory administration system comprises a plurality of components and at least one communication conduit is configured to communicably couple between two or more components of the memory administration system.
6. The quantum processor of claim 1 wherein the demultiplexer circuit administers digital signals.
7. The quantum processor of claim 6 wherein the memory administration system includes a digital-to-analog converter (DAC).
8. The quantum processor of claim 7 wherein the demultiplexer circuit communicably couples to the DAC to administer a digital signal thereto.
9. The quantum processor of claim 8 wherein the demultiplexer circuit administers digital signals in the form of discrete magnetic flux quanta, and the DAC includes a superconducting flux DAC.
10. The quantum processor of claim 8 wherein the DAC communicably couples an analog signal to at least one programmable device.
11. The quantum processor of claim 1 wherein the demultiplexer circuit includes a plurality of routing devices.
12. The quantum processor of claim 1 wherein the plurality of routing devices are arranged in logical rows to form a logical binary tree.
13. A method of programming a quantum processor, wherein the quantum processor includes a plurality of programmable devices and a memory administration system having a demultiplexer circuit, the method comprising:
using the demultiplexer circuit to route a first signal to a first programmable device, wherein the first signal embodies a first control parameter for the first programmable device; and
administering the first signal to the first programmable device.
14. The method of claim 13 wherein the first signal is a digital signal and the memory administration system includes a digital-to-analog converter (DAC), the method further comprising:
routing the digital signal to the DAC by the demultiplexer;
administering the digital signal from the demultiplexer circuit to the DAC;
converting the digital signal to an analog signal by the DAC; and
administering the analog signal from the DAC to the first programmable device.