Integrity checking of configuration data of programmable device

1. A method of operating a programmable device, the method comprising:

loading an original configuration data to configuration registers of the programmable device, wherein the original configuration data comprises data to establish a plurality of functional blocks in the programmable device to perform user-defined logic functions;

accessing first master redundancy check (RC) data corresponding to an RC operation of the original configuration;

accessing second master RC data corresponding to an RC operation of the original configuration;

comparing the first master RC data with the second master RC data;

performing a first exception action if the second master RC data does not match with the first master RC data;

generating current RC data by performing a RC operation of a current configuration data of the configuration registers of the programmable device;

comparing the current RC data with the first master RC data; and

performing a second exception action if the current RC data does not match with the first master RC data.

2. The method of claim 1 , wherein the configuration data comprises additional data to configure input/output resources.

3. The method of claim 1 , wherein the configuration data comprises additional data to configure programmable analog blocks.

4. The method of claim 1 , wherein the configuration data comprises additional data to configure routing resources.

5. The method of claim 1 , further comprising repeatedly generating and comparing the current RC and performing the second exception action when the current RC data does not match with the first master RC data.

6. The method of claim 1 , wherein the generating of the current RC data is controlled by a direct memory access (DMA) controller.

7. The method of claim 1 , wherein the RC data is at least one of a checksum, cyclic redundancy check (CRC) data, horizontal redundancy check data, vertical redundancy check data or a cryptographic message digest.

8. A method of operating a programmable device, the method comprising:

loading an original configuration data to configuration registers of the programmable device, wherein the original configuration data comprises data to establish a plurality of functional blocks in the programmable device to perform user-defined logic functions;

performing a redundancy check (RC) of the original configuration data to produce a first master RC data;

performing a RC of the original configuration data to produce a second master RC data;

comparing the second master RC data with the first master RC data to determine whether there is a mismatch between the second master RC data and the first master RC data;

performing a RC of a current configuration data of the configuration registers to produce a current RC data; and

comparing the current RC data with the first master RC data to determine whether there is a mismatch between the current RC data and the first master RC data.

9. The method of claim 8 , wherein the configuration data comprises additional data to configure input/output resources.

10. The method of claim 8 , wherein the redundancy check of the original configuration data or the current configuration data is performed using a direct access memory (DMA) controller.

11. The method of claim 8 , wherein the configuration data comprises additional data to configure programmable analog blocks.

12. The method of claim 8 , wherein the configuration data comprises additional data to configure routing resources.

13. The method of claim 8 , where comparing the second master RC data to the first master RC data and comparing the current master RC data to the first master RC data is performed iteratively.

14. A system of operating a programmable device, the system comprising:

a redundancy check (RC) generator to perform RC operations;

a first memory to store first master RC data obtained through performing a first RC operation of original configuration data initially loaded to configuration registers of the programmable device, wherein the configuration registers comprise registers to store data to establish a plurality of functional blocks in the programmable device to perform user-defined logic functions;

a second memory to store second master RC data obtained through performing a second RC operation of the original configuration data;

a third memory to store a current RC data obtained through performing a third RC operation of current configuration data of the configuration registers; and

a comparator module to compare the second master RC data to the first master RC data and to compare the current RC data to the first master RC data.

15. The system of claim 14 , wherein the configuration registers comprise additional registers to store additional data to configure input/output resources.

16. The system of claim 15 , further comprising a direct memory access (DMA) controller coupled to the first memory and the second memory to access the master RC data and the current RC data.

17. The system of claim 15 , wherein the master RC data and the current RC data are at least one of a checksum, cyclic redundancy check (CRC) data, horizontal redundancy check data, vertical redundancy check data or a cryptographic message digest.

18. The system of claim 15 , wherein comparator module is configured to generate an exception signal when the current RC data does not match with the master RC data.

19. The system of claim 14 , wherein the configuration registers comprise additional registers to store additional data to configure programmable analog blocks.

20. The system of claim 14 , wherein the configuration registers comprise additional registers to store additional data to configure routing resources.