Dynamic CPU voltage regulator phase shedding
View Patent ↗A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization information, determine whether to adjust a performance state, lookup voltage regulator information for new performance state, adjust active voltage regulator phase, and adjust performance state. The voltage regulator phase shedding system can also include one or more subsystems to read a power measurement, calculate throttling requirements, determine whether to adjust a throttling, lookup voltage regulator information for new performance state capacity, adjust active voltage regulator phase, and adjust throttling.
1. A system, comprising:
a processor;
a voltage regulator coupled to the processor; and
a non-transitory, computer-readable medium that is coupled to the processor and the voltage regulator and that includes instructions that provide a management system that is configured to:
receive a first active performance state (P-state) of the processor;
determine that the voltage regulator is operating at a first efficiency with the processor operating in the first active P-state; and
determine that shedding at least one active processor voltage regulator phase will cause the operation of the voltage regulator to shift to a second efficiency that is higher than the first efficiency and, in response, cause the voltage regulator to shed the at least one active processor voltage regulator phase while the processor remains in an active P-state.
2. The system of claim 1 , wherein the management system is operating system independent.
3. The system of claim 1 , wherein the management system is Basic Input/Output System (BIOS) based.
4. The system of claim 1 , wherein the causing the voltage regulator to shed at least one active processor voltage regulator phase is performed to match a maximum allowable load of the processor.
5. The system of claim 1 , wherein the causing the voltage regulator to shed at least one active processor voltage regulator phase results in a load of the processor shifting such that the operation of the voltage regulator shifts to the second efficiency.
6. The system of claim 1 , wherein the causing the voltage regulator to shed at least one active processor voltage regulator phase such that the operation of the voltage regulator shifts to the second efficiency is performed at the intersection of efficiency curves for phases of the voltage regulator.
7. An information handling system (IHS) comprising:
an IHS component that is operating in a first active performance state (P-state);
a voltage regulator coupled to the IHS component; and
a non-transitory, computer-readable medium that is coupled to the IHS component and the voltage regulator, wherein the non-transitory, computer-readable medium includes instructions that provide a management system that is configured to:
determine that the voltage regulator will operate more efficiently with the IHS component operating at a second active P-state relative to the first active P-state if at least one additional active voltage regulator phase is enabled and, in response, enable the at least one active voltage regulator phase in the voltage regulator; and
switch the IHS component from the first active P-state to the second active P-state subsequent to enabling the at least one active voltage regulator phase.
8. The IHS of claim 7 , wherein the management system is further configured to:
determine that the voltage regulator is operating at a first efficiency with the IHS component operating in the second active P-state; and
cause the voltage regulator to enable at least one active voltage regulator phase, wherein, in response to the enabling, the voltage regulator operation shifts to a second efficiency that is higher than the first efficiency.
9. The IHS of claim 7 , wherein the management system is operating system independent.
10. A method, comprising:
receiving, by a management system that is provided using instructions included on a non-transitory computer-readable medium, a first active performance state (P-state) of a processor;
determining, by the management system, that a voltage regulator is operating at a first efficiency with the processor operating in the first active P-state; and
determining, by the management system, that shedding at least one active processor voltage regulator phase will cause the operation of a voltage regulator to shift to a second efficiency that is higher than the first efficiency and, in response, causing the voltage regulator to shed the at least one active processor voltage regulator phase while the processor remains in an active P-state.
11. The method of claim 10 , further comprising:
determining, by the management system, that the processor is switching to a second active P-state that includes a higher load than the first active P-state; and
determining, by the management system, that the voltage regulator will operate more efficiently at the higher load relative to the operation of the voltage regulator with the processor operating in first active P-state if at least one additional active processor voltage regulator phase is enabled and, in response, enabling the at least one additional active processor voltage regulator phase while the processor remains in an active P-state.
12. The method of claim 11 , further comprising:
switching, by the management system, the processor to the second active P-state subsequent to enabling the at least one active processor voltage regulator phase.
13. A processor performance state (P-state) management system, comprising:
a processor;
a voltage regulator coupled to the processor; and
a non-transitory, computer-readable medium that is coupled to the processor and the voltage regulator and that includes instructions that provide a management system that is configured to:
calculate throttling requirements for the processor using throttling information, wherein the calculating is performed while the processor is in an active performance state (P-state);
determine voltage regulator phase efficiency information for the voltage regulator based on the throttling requirements;
adjust at least one active voltage regulator phase for the voltage regulator using the voltage regulator phase efficiency information that is based on the throttling requirements for the processor; and
perform a throttling operation according to the throttling requirements subsequent to adjusting the at least one active voltage regulator phase, wherein the processor remains in an active P-state subsequent to the throttling operation.
14. The system of claim 13 , wherein the throttling requirements include decreasing the throttling.
15. The system of claim 14 , wherein the adjusting the at least one active voltage regulator phase includes enabling at least one active voltage regulator phase in response to the decreased throttling requirements.
16. The system of claim 15 , wherein the management system is configured to:
retrieve requirements for a P-state cap, wherein the at least one active voltage regulator phase is enabled according to the requirements.
17. The system of claim 13 , wherein the throttling requirements include increasing the throttling.
18. The system of claim 17 , wherein the adjusting the at least one active voltage regulator phase includes shedding at least one active voltage regulator phase in response to the increased throttling requirements.
19. The system of claim 18 , wherein the management system is configured to:
retrieve requirements for a P-state cap, wherein the at least one active voltage regulator phase is shed according to the requirements.