IP Library Granted Patent US 8,645,663
Granted Patent B2
US 8,645,663 · App. 13/229,772 · Granted Feb 4, 2014

Network interface controller with flexible memory handling

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Quick Facts
Patent No.
US 8,645,663
App. No.
13/229,772
Granted
Feb 4, 2014
Kind
B2
Abstract

An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.

Claims (44)

1. An input/output (I/O) device, comprising:

a host interface for connection to a host device having a memory;

a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory; and

processing circuitry, which is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory,

wherein at least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.

2. The device according to claim 1 , wherein the processing circuitry is configured to translate the virtual addresses into the physical addresses by accessing a translation table using the memory keys.

3. The device according to claim 1 , wherein the multiple respective ranges are mutually non-contiguous.

4. The device according to claim 3 , wherein the I/O operation referencing the indirect memory key contains a reference to a single contiguous memory segment at a specified address, and

wherein the processing circuitry is configured, using the memory keys, to translate the reference so as to identify and access respective segments of the memory in at least two of the mutually non-contiguous ranges in performing the I/O operation.

5. The device according to claim 1 , wherein the memory keys comprise a further indirect memory key, which points to one or more other indirect memory keys.

6. The device according to claim 1 , wherein the processing circuitry has multiple work queues, which are respectively assigned to software applications and which comprise at least one work queue that is configured to receive from a respective software application at least:

a first work request instructing the I/O device to register a range of virtual addresses in the memory for use in serving the respective software application; and

a second work request instructing the I/O device to perform the I/O operation with respect to a specified address in the registered range, and

wherein the processing circuitry is configured to execute the work requests so as to cause the network interface to transmit and receive over the network data packets associated with the I/O operation.

7. The device according to claim 6 , wherein the software application is configured to run on a virtual machine in a guest domain on the host device, and wherein the physical addresses belong to the guest domain, and

wherein the processing circuitry is configured to translate the physical addresses belonging to the guest domain into machine addresses for use in accessing the memory.

8. The device according to claim 6 , wherein the processing circuitry is configured to translate the virtual addresses into the physical addresses using a translation table, and wherein the first work request provides a memory key for accessing the translation table.

9. The device according to claim 6 , wherein the processing circuitry is configured to return a completion queue element to the respective software application to indicate that the range of the virtual addresses has been registered in response to the first work request.

10. The device according to claim 6 , wherein the I/O operation invoked by the second work request comprises a remote direct memory access (RDMA) operation.

11. The device according to claim 1 , wherein the direct memory keys are registered on the I/O device by a driver program associated with an operating system on the host device, and

wherein the indirect memory keys are registered by software applications.

12. A method for communication, comprising:

coupling an input/output (I/O) device to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in a memory of a host device that is coupled to the I/O device;

receiving in the I/O device memory keys, wherein at least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, which are associated with respective ranges of the virtual addresses;

translating, in the I/O device, the specified virtual addresses into physical addresses using the memory keys; and

performing an I/O operation referencing the indirect memory key by accessing the physical addresses in the memory corresponding to at least two of the respective ranges of the virtual addresses that are associated with the direct memory keys that are pointed to by the indirect memory key.

13. The method according to claim 12 , wherein the specified virtual addresses are translated into the physical addresses by accessing a translation table using the memory keys.

14. The method according to claim 12 , wherein the multiple respective ranges are mutually non-contiguous.

15. The method according to claim 14 , wherein the I/O operation referencing the indirect memory key contains a reference to a single contiguous memory segment at a specified address, and

wherein translating the specified virtual addresses comprises translating the reference so as to identify and access respective segments of the memory in at least two of the mutually non-contiguous ranges in performing the I/O operation.

16. The method according to claim 12 , wherein the memory keys comprise a further indirect memory key, which points to one or more other indirect memory keys.

17. The method according to claim 12 , and comprising:

respectively assigning multiple work queues in the I/O device to software applications running over an operating system on the host device;

receiving in at least one work queue of the I/O device, from a respective software application, at least:

a first work request instructing the I/O device to register a range of virtual addresses in a memory of the host device for use by the respective software application; and

a second work request instructing the I/O device to perform the I/O operation with respect to a specified address in the registered range; and

executing the work requests in the single work queue so as to cause the I/O device to transmit and receive over the network data packets associated with the I/O operation.

18. The method according to claim 17 , wherein the software application is configured to run on a virtual machine in a guest domain on the host device, and wherein the physical addresses belong to the guest domain, and

wherein translating the virtual addresses comprises translating the physical addresses belonging to the guest domain into machine addresses for use in accessing the memory.

19. The method according to claim 17 , wherein the virtual addresses are translated into the physical addresses using a translation table, and wherein the first work request provides a memory key for accessing the translation table.

20. The method according to claim 17 , wherein executing the work requests comprises returning a completion queue element to the respective software application to indicate that the range of the virtual addresses has been registered in response to the first work request.

21. The method according to claim 17 , wherein executing the work requests comprises executing a remote direct memory access (RDMA) operation responsively to the second work request.

22. The method according to claim 12 , wherein the direct memory keys are registered on the I/O device by a driver program associated with an operating system on the host device, and

wherein the indirect memory keys are registered by software applications.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 37900/0720 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 046542/0792 →
PATENT SECURITY AGREEMENT Recorded Feb 24, 2016
From: MELLANOX TECHNOLOGIES, LTD.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 037900/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2011
From: KAGAN, MICHAEL; SHAHAR, ARIEL; BLOCH, NOAM
To: MELLANOX TECHNOLOGIES LTD.
Reel/Frame 026884/0647 →