Memory controller and data processing system
View Patent ↗A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
1. A semiconductor device comprising:
a memory controller coupled to a volatile memory which has a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, the volatile memory being controlled to pre-charge the plurality of bit lines after a read access in a first mode and not to pre-charge the plurality of bit lines after a read access in a second mode, and including a counter which counts a number of successive accesses to different word lines; and
a central processing unit controlling the memory controller,
wherein the memory controller changes from the second mode to the first mode after different word lines are accessed a predetermined number of times successively, a number of the predetermined time being set in the counter, and
wherein the central processing unit and the memory controller are provided in a first semiconductor chip.
2. The semiconductor device according to claim 1 ,
wherein the first mode is a page-on mode, and
wherein the second mode is a page-off mode.
3. The semiconductor device according to claim 1 ,
wherein the volatile memory is a DRAM.
4. The semiconductor device according to claim 3 ,
wherein the first mode is a page-on mode, and
wherein the second mode is a page-off mode.
5. The semiconductor device according to claim 1 ,
wherein the volatile memory is provided in a second semiconductor chip different from the first semiconductor chip.
6. The semiconductor device according to claim 5 ,
wherein the first mode is a page-on mode, and
wherein the second mode is a page-off mode.
7. The semiconductor device according to claim 5 ,
wherein the volatile memory is a DRAM.
8. The semiconductor device according to claim 7 ,
wherein the first mode is a page-on mode, and
wherein the second mode is a page-off mode.
9. The semiconductor device according to claim 5 ,
wherein the first semiconductor chip and the second semiconductor chip are mounted in a same package.
10. The semiconductor device according to claim 9 ,
wherein the first mode is a page-on mode, and
wherein the second mode is a page-off mode.
11. The semiconductor device according to claim 9 ,
wherein the volatile memory is a DRAM.
12. The semiconductor device according to claim 11 ,
wherein the first mode is a page-on mode, and
wherein the second mode is a page-off mode.
13. The semiconductor device according to claim 1 ,
wherein the volatile memory is provided in the first semiconductor chip together with the memory controller and the central processing unit.
14. The semiconductor device according to claim 13 ,
wherein the first mode is a page-on mode, and
wherein the second mode is a page-off mode.
15. The semiconductor device according to claim 13 ,
wherein the volatile memory is a DRAM.
16. The semiconductor device according to claim 15 ,
wherein the first mode is a page-on mode, and
wherein the second mode is a page-off mode.