Power semiconductor devices and fabrication methods

1. A double RESURF semiconductor device having an n-drift region with a p-top layer, and wherein a MOS (Metal Oxide Semiconductor) channel of said device is formed within said p-top layer, wherein said p-top layer comprises a first p-top portion in or adjacent said n-drift region, and a second p-top portion adjacent to an n + region or p-well region of a source structure of said device, and wherein the first and second p-top portions are laterally spaced to one another and wherein the device is configured such that a surface field of said n-drift region of said device is reduced by said first p-top region when said device is off and in a blocking mode.

2. A double RESURF semiconductor device as claimed in claim 1 wherein said source structure comprises said n + region, a source connection to said n + region and a p-well beneath said n + region, wherein said n-drift region is bonded laterally by said p-well, and wherein said second p-top portion extends above said n-drift region and is shallower than said p-well.

3. A double RESURF semiconductor device as claimed in claim 1 wherein said second p-top portion further comprises a threshold adjust implant.

4. A double RESURF semiconductor device as claimed in claim 1 , further comprising a high voltage structure, wherein said high voltage structure comprises an n-well and a high voltage connection to said n-well, and wherein said n-drift region extends to said n-well of said high voltage structure.

5. A double RESURF semiconductor device as claimed in claim 4 wherein said device is an LDMOSFET.

6. A double RESURF semiconductor device as claimed in claim 4 wherein said device is an LIGBT and wherein said high voltage structure further comprises a p + region within said n-well electrically connected to said high voltage connection of said device.

7. A double RESURF semiconductor device as claimed in claim 1 further comprising a gate oxide layer over said second p-top portion and over a portion of said n-drift region laterally between said first and second p-top portions, a field oxide layer over said first p-top portion, and a gate electrode over said gate oxide and field oxide layers and above at least said second p-top portion.

8. A double RESURF semiconductor device as claimed in claim 7 wherein said gate electrode is also above said portion of said n-drift region laterally between said p-top portions.

9. A double RESURF semiconductor device as claimed in claim 7 wherein said gate electrode is above an n + region between said first and second p-top portions.

10. A double RESURF semiconductor device as claimed in claim 7 wherein the device is configured such that when a high voltage is applied across said n-drift region a flow of current through said n-drift region is controlled by applying a voltage to a gate electrode of said MOS channel to control a current flow through a channel at the surface of said second p-top portion.

11. A double RESURF semiconductor device as claimed in claim 1 wherein said p-top layer has a lateral gap comprising an n-type region, and wherein to one lateral side of said gap said p-top region comprises a MOS channel of said semiconductor device and to an opposite lateral side of said gap said p-top region comprises an n-drift region surface-field reducing part of said semiconductor device.

12. A double RESURF semiconductor device as claimed in claim 1 wherein said substrate is an SOI substrate with a buried oxide layer beneath said n-drift region.

13. A double RESURF semiconductor device as claimed in claim 12 wherein an opening is provided beneath a portion of said buried oxide layer beneath said n-drift region such that said buried oxide beneath said n-drift region is suspended by an adjacent portion of said substrate.