CMOS image sensor
View Patent ↗A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.
1. A circuit comprising:
a plurality of transistors including:
a first transistor configured to reset a photodiode,
a second transistor configured to receive a charge from the photodiode and to output an amplified signal, and
a third transistor configured to transfer the amplified signal to a column line;
wherein at least one source of the plurality of transistors or at least one drain of the plurality of transistors is configured to receive a first voltage;
wherein at least one gate of the plurality of transistors is configured to receive a second voltage; and
wherein the second voltage is less than the first voltage.
2. The circuit of claim 1 , further comprising a switching device configured to selectively provide the second voltage to the at least one gate of the plurality of transistors.
3. The circuit of claim 2 , wherein the switching device comprises an NMOS transistor.
4. The circuit of claim 3 , wherein the switching device comprises a threshold voltage of approximately zero.
5. The circuit of claim 1 , wherein the first voltage is approximately 0.7 volts greater than the second voltage.
6. The circuit of claim 1 , wherein the first voltage comprises approximately 2.5 volts and the second voltage comprises approximately 1.8 volts.
7. The circuit of claim 1 , wherein the at least one gate of the plurality of transistors is a gate of the third transistor.
8. A circuit comprising:
a plurality of transistors including:
a first transistor configured to reset a photodiode,
a second transistor configured to receive a charge from the photodiode and to output an amplified signal,
a third transistor configured to transfer the amplified signal to a column line, and
a fourth transistor configured to transfer the charge from the photodiode to the second transistor;
wherein at least one source of the plurality of transistors or at least one drain of the plurality of transistors is configured to receive a first voltage;
wherein at least one gate of the plurality of transistors is configured to receive a second voltage; and
wherein the second voltage is less than the first voltage.
9. The circuit of claim 8 , further comprising a switching device configured to selectively provide the second voltage to the at least one gate of the plurality of transistors.
10. The circuit of claim 9 , wherein the switching device comprises an NMOS transistor.
11. The circuit of claim 10 , wherein the switching device comprises a threshold voltage of approximately zero.
12. The circuit of claim 8 , wherein the first voltage is approximately 0.7 volts greater than the second voltage.
13. The circuit of claim 8 , wherein the first voltage comprises approximately 2.5 volts and the second voltage comprises approximately 1.8 volts.
14. The circuit of claim 8 , wherein the at least one gate of the plurality of transistors is a gate of the third transistor.
15. A method for operating a circuit, the method comprising:
receiving a first voltage by at least one source or at least one drain of a plurality of transistors;
receiving a second voltage by at least one gate of the plurality of transistors;
wherein the second voltage is less than the first voltage; and
wherein the plurality of transistors includes:
a first transistor configured to reset a photodiode,
a second transistor configured to receive a charge from the photodiode and to output an amplified signal, and
a third transistor configured to transfer the amplified signal to a column line.
16. The method of claim 15 , wherein said receiving a second voltage by at least one gate of the plurality of transistors further comprises switching a switching device to selectively provide the second voltage to the at least one gate of the plurality of transistors.
17. The method of claim 16 , wherein the switching device comprises an NMOS transistor.
18. The method of claim 17 , wherein the switching device comprises a threshold voltage of approximately zero.
19. The method of claim 15 , wherein the first voltage is approximately 0.7 volts greater than the second voltage.
20. The method of claim 15 , wherein the at least one gate of the plurality of transistors is a gate of the third transistor.