Scalable processing unit
View Patent ↗Various methods and systems are provided for processing units that may be scaled. In one embodiment, a processing unit includes a plurality of scalar processing units and a vector processing unit in communication with each of the plurality of scalar processing units. The vector processing unit is configured to coordinate execution of instructions received from the plurality of scalar processing units. In another embodiment, a scalar instruction packet including a pre-fix instruction and a vector instruction packet including a vector instruction is obtained. Execution of the vector instruction may be modified by the pre-fix instruction in a processing unit including a vector processing unit. In another embodiment, a scalar instruction packet including a plurality of partitions is obtained. The location of the partitions is determined based upon a partition indicator included in the scalar instruction packet and a scalar instruction included in a partition is executed by a processing unit.
1. A processing unit, comprising:
a plurality of scalar processing units; and
a vector processing unit in communication with each of the plurality of scalar processing units, the vector processing unit configured to coordinate parallel execution of instructions received from the plurality of scalar processing units by time multiplexing, wherein a plurality of instructions received in a same clock cycle from separate scalar processing units are queued for execution based upon a predetermined ordering of the plurality of scalar processing units.
2. The processing unit of claim 1 , wherein the predetermined ordering is a round robin ordering of the plurality of scalar processing units.
3. The processing unit of claim 1 , wherein the plurality of instructions received in the same clock cycle are allowed to be queued for execution based upon a predetermined ranking of the plurality of scalar processing units.
4. The processing unit of claim 1 , wherein the vector processing unit comprises a number of pixel processing units including eight or less active pixel processing units.
5. The processing unit of claim 4 , wherein the number of pixel processing units is based upon a defined vector processing unit performance.
6. A chip, comprising:
a plurality of scalar processing units; and
a vector processing unit in communication with each of the plurality of scalar processing units, the vector processing unit configured to coordinate parallel execution of instructions received from the plurality of scalar processing units by time multiplexing, wherein a plurality of instructions received in a same clock cycle from separate scalar processing units are queued for execution based upon a predetermined ordering of the plurality of scalar processing units.
7. The chip of claim 6 , wherein the predetermined ordering is a round robin ordering of the plurality of scalar processing units.
8. The chip of claim 6 , wherein the plurality of instructions received in the same clock cycle are allowed to be queued for execution based upon a predetermined ranking of the plurality of scalar processing units.
9. The chip of claim 6 , wherein the vector processing unit comprises a plurality of pixel processing units (PPUs), where a portion of the plurality of PPUs are deactivated.
10. The chip of claim 9 , wherein the plurality of PPUs includes a number of active PPUs, the number of active PPUs based at least in part upon loading of the vector processing unit.
11. The chip of claim 10 , wherein the number of active PPUs based upon a quantity of queued instructions waiting to be executed.
12. The chip of claim 10 , wherein the active PPUs of the plurality of PPUs execute instructions in a plurality of clock cycles.
13. A method, comprising:
receiving, by a vector processing unit, instructions from a plurality of scalar processing units in a clock cycle; and
queuing, by the vector processing unit, the instructions from the plurality of scalar processing units to coordinate parallel execution of the instructions by time multiplexing, wherein a plurality of instructions received in a same clock cycle from separate scalar processing units are queued for execution based upon a predetermined ordering of the plurality of scalar processing units.
14. The method of claim 13 , wherein the predetermined ordering is a round robin ordering of the plurality of scalar processing units.
15. The method of claim 13 , wherein the plurality of instructions received in the same clock cycle are queued based upon a predetermined ranking of the plurality of scalar processing units.
16. The processing unit of claim 1 , wherein a scalability of the vector processing unit is allowed to be moved downward to enable smaller blocks than a vector length are operated upon, and wherein the vector length is associated with a platform or a die space.
17. The processing unit of claim 1 , wherein tags are allowed to be passed to the vector processing unit to indicate the scalar processing unit that corresponds to the instruction performed by the vector processing unit.
18. The method of claim 13 , further comprising allowing a scalability of the vector processing unit to be moved downward to enable operation upon smaller blocks than a vector length, and wherein the vector length is associated with a platform or a die space.
19. The method of claim 13 , wherein tags are allowed to be passed to the vector processing unit to indicate the scalar processing unit that corresponds to the instruction performed by the vector processing unit.
20. The chip of claim 6 , wherein tags are allowed to be passed to the vector processing unit to indicate the scalar processing unit that corresponds to the instruction performed by the vector processing unit.
21. The chip of claim 6 , wherein a scalability of the vector processing unit is allowed to be moved downward to enable smaller blocks than a vector length are operated upon,
and wherein the vector length is associated with a platform or a die space.