Transimpedance amplifier and method thereof
A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node.
1. An apparatus comprising:
a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node;
a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS transistor, wherein a gate terminal of the MOS transistor is coupled to a drain terminal of the MOS transistor via a resistor; and
a current mirror for receiving a third current from a third circuit node and outputting the first current to the first circuit node.
2. The apparatus of claim 1 , wherein a drain terminal of the MOS transistor is coupled to the second circuit node and a source terminal of the MOS transistor is coupled to a substantially fixed potential node.
3. The apparatus of claim 1 , wherein a source terminal of the MOS transistor is coupled to the second circuit node and the drain terminal of the MOS transistor is coupled to a substantially fixed potential node.
4. The apparatus of claim 1 further comprising a biasing circuit for outputting a substantially fixed current to the first circuit node, wherein a current-mode input is injected to the first circuit node.
5. The apparatus of claim 4 , wherein the biasing circuit is a current source.
6. The apparatus of claim 1 further comprising:
a biasing circuit for outputting a substantially fixed current to the third circuit node, wherein a current-mode input is injected to the third circuit node.
7. The apparatus of claim 6 , wherein the current mirror comprises a first MOS transistor configured in a diode-connected configuration for converting the third current into a voltage signal and a second MOS transistor configured in a common-source amplifier configuration for converting the voltage signal into the first current.
8. The apparatus of claim 7 , wherein the first MOS transistor and the second MOS transistor have the same width-to-length ratio so that the first current is substantially equal to the third current.
9. The apparatus of claim 7 , wherein a gain of the apparatus is adjusted by choosing a width-to-length ratio of the second MOS transistor that is different from a width-to-length ratio of the first MOS transistor.
10. The apparatus of claim 1 , wherein the resistor is sufficiently large to provide isolation between the gate terminal of the diode-connected MOS transistor and the second circuit node.
11. A method comprising:
receiving a first current from a first circuit node;
amplifying the first current using a common-gate amplifier to output a second current to a second circuit node;
converting the second current into a voltage-mode output at the second circuit node by using a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS transistor, wherein a gate terminal of the MOS transistor is coupled to a drain terminal of the MOS transistor via a resistor; and
converting a third current from a third circuit node into the first current using a current mirror.
12. The method of claim 11 , wherein the drain terminal of the MOS transistor is coupled to the second circuit node and a source terminal of the MOS transistor is coupled to a substantially fixed potential node.
13. The method of claim 11 , wherein a source terminal of the MOS transistor is coupled to the second circuit node and the drain terminal of the MOS transistor is coupled to a substantially fixed potential node.
14. The method of claim 11 further comprising:
injecting a current-mode input into the first circuit node; and
establishing a substantially constant current to the first circuit node using a current source.
15. The method of claim 11 further comprising:
injecting a current-mode input into a third circuit node; and
establishing a substantially constant current to the third circuit node using a current source.
16. The method of claim 15 , wherein the current mirror comprises: a first MOS transistor configured in a diode-connected configuration for converting the third current into a voltage signal; and a second MOS transistor configured in a common-source amplifier configuration for converting the voltage signal into the first current.
17. The method of claim 16 further comprising adjusting a gain of the current mirror by adjusting a ratio of the width-to-length ratio of the second MOS transistor to the width-to-length ratio of the first MOS transistor.