System and method for managing erase operations in a non-volatile memory
View Patent ↗Embodiments of the invention are directed to managing a memory component. A method may include performing a first erase operation according to a first set of erase parameters, determining a result of the first erase operation, modifying the first set erase parameters based on the result to produce a second set of erase parameters and performing a second erase operation according to a second set of erase parameters. A condition parameter may be maintained based on the erased parameters and/or based on a result of an erase procedure.
1. A method of managing information in a set of flash memory cells included in a memory block, the method comprising:
performing a first erase operation, the operation including applying a first number of erase pulses to the memory block;
calculating an erase indicator based on counting flash memory cells storing data;
based on the erase indicator, determining a second number of erase pulses; and
performing a second erase operation including the second number of erase pulses.
2. The method of claim 1 , comprising:
performing the first erase operation according to a first erase voltage level;
based on the erase indicator, determining a second erase voltage level; and
performing the second erase operation according to the second erase voltage level.
3. The method of claim 1 , comprising:
performing the first erase operation according to a first pulse duration parameter;
based on the erase indicator, determining a second pulse duration parameter;
and
performing the second erase operation according to the second pulse duration parameter.
4. The method of claim 1 , comprising:
performing the first erase operation according to a set of erase control parameters associated with the memory block;
based on the erase indicator, updating the set of erase control parameters to produce an updated set of erase control parameters; and
performing the second erase operation according to the updated set of erase control parameters.
5. The method of claim 1 , comprising:
updating a condition parameter associated with the memory block based on the number of pulses applied to the block;
determining an error threshold based on the condition parameter; and
terminating an erase procedure based on the error threshold.
6. The method of claim 1 , comprising:
updating a condition parameter associated with the memory block based on the set of erase parameters applied to the block;
determining an error threshold based on the condition parameter; and
terminating an erase procedure based on the error threshold.
7. The method of claim 1 , comprising:
storing information defining the position of bits that were improperly erased; and
decoding the bits using the position information to reduce the probability of decoding failure.
8. A controller for managing information in a set of flash memory cells included in a memory block, the controller having stored thereon instructions that when executed cause the controller to:
perform a first erase operation, the operation including applying a first number of erase pulses to the memory block;
calculate an erase indicator based on counting flash memory cells storing data;
based on the erase indicator, determine a second number of erase pulses; and
perform a second erase operation including the second number of erase pulses.
9. The controller of claim 8 , wherein the instructions when executed further cause the controller to:
perform the first erase operation according to a first erase voltage level;
based on the erase indicator, determine a second erase voltage level; and
perform the second erase operation according to the second erase voltage level.
10. The controller of claim 8 , wherein the instructions when executed further cause the controller to:
perform the first erase operation according to a first pulse duration parameter;
based on the erase indicator, determine a second pulse duration parameter; and
perform the second erase operation according to the second pulse duration parameter.
11. The controller of claim 8 , wherein the instructions when executed further cause the controller to:
perform the first erase operation according to a set of erase control parameters associated with the memory block;
based on the erase indicator, update the set of erase control parameters to produce an updated set of erase control parameters; and
perform the second erase operation according to the updated set of erase control parameters.
12. The controller of claim 8 , wherein the instructions when executed further cause the controller to:
update a condition parameter associated with the memory block based on the number of pulses applied to the block;
determine an error threshold based on the condition parameter; and
terminate an erase procedure based on the error threshold.
13. The controller of claim 8 , wherein the instructions when executed further cause the controller to:
update a condition parameter associated with the memory block based on the set of erase parameters applied to the block;
determine an error threshold based on the condition parameter; and
terminate an erase procedure based on the error threshold.
14. The controller of claim 8 , wherein the instructions when executed further cause the controller to:
store information defining the position of bits that were improperly erased; and
decode the bits using the position information to reduce the probability of decoding failure.
15. A system comprising:
a memory unit comprising a plurality of memory blocks, wherein each memory block comprises a set of memory cells; and
a controller to manage information in each set of memory cells, whereing the controller is to:
perform a first erase operation, the operation including applying a first number of erase pulses to the memory block;
calculate an erase indicator based on counting memory cells storing data;
based on the erase indicator, determine a second number of erase pulses; and
perform a second erase operation including the second number of erase pulses.
16. The system of claim 15 , wherein the controller is to:
perform the first erase operation according to a first erase voltage level;
based on the erase indicator, determine a second erase voltage level; and
perform the second erase operation according to the second erase voltage level.
17. The system of claim 15 , wherein the controller is to:
perform the first erase operation according to a first pulse duration parameter;
based on the erase indicator, determine a second pulse duration parameter; and
perform the second erase operation according to the second pulse duration parameter.
18. The system of claim 15 , wherein the controller is to:
perform the first erase operation according to a set of erase control parameters associated with the memory block;
based on the erase indicator, update the set of erase control parameters to produce an updated set of erase control parameters; and
perform the second erase operation according to the updated set of erase control parameters.
19. The system of claim 15 , wherein the controller is to:
update a condition parameter associated with the memory block based on the number of pulses applied to the block;
determine an error threshold based on the condition parameter; and
terminate an erase procedure based on the error threshold.
20. The system of claim 15 , wherein the memory unit is a flash memory unit comprising flash memory cells.