Delay circuit and inverter for semiconductor integrated device
View Patent ↗An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has high and low potential parts. The low potential part includes a pair of FETs. A source terminal of one FET is connected to a drain terminal of the other FET at a first common node. The high potential part includes another pair of FETs, with a source terminal of one FET being connected to a drain terminal of the other FET at a second common node. A power supply potential is applied to the first common node when the inverter output becomes a high potential. A ground potential is applied to the second common node when the inverter output becomes a low potential.
1. A delay circuit of a semiconductor integrated device comprising:
a plurality of inverters connected in cascade, each said inverter including:
a pair of first FETs that each have a channel of a first conductivity type, a drain of one of the first FETs and a source of the other being connected to each other at a first connection node, gates of both the first FETs being connected to each other at an input node, a first potential being always applied to a source of the one of the first FETs as long as the semiconductor integrated device is in operation, and a drain of the other being connected to an output node;
a pair of second FETs that each have a channel of a second conductivity type, a drain of one of the second FETs and a source of the other being connected to each other at a second connection node, gates of both the second FETs being connected to each other at the input node, a second potential being always applied to a source of the one of the second FETs as long as the semiconductor integrated device is in operation, and a drain of the other being connected to the output node;
a first additional FET that applies the second potential to the first connection node when a potential at the output node becomes the second potential;
a second additional FET that always supplies the second potential to the first additional FET as long as the semiconductor integrated device is in operation;
a third additional FET whose source receives the first potential and whose drain is connected to a gate of the second additional FET;
a fourth additional FET whose source receives the second potential and whose gate and drain are both connected to a gate of the third additional FET;
a fifth additional FET that applies the first potential to the second connection node when a potential at the output node becomes the first potential;
a sixth additional FET that always supplies the first potential to the fifth additional FET as long as the semiconductor integrated device is in operation;
a seventh additional FET whose source receives the second potential and whose drain is connected to a gate of the sixth additional FET; and
an eighth additional FET whose source receives the first potential and whose gate and drain are both connected to a gate of the seventh additional FET.
2. The delay circuit of a semiconductor integrated device according to claim 1 , wherein the first potential is applied to the source of the one of the first FETs through a first resistor, and the second potential is applied to the source of the one of the second FETs through a second resistor.
3. The delay circuit of a semiconductor integrated device according to claim 2 , wherein the first resistor has a variable resistance, and the second resistor has a variable resistance.
4. The delay circuit of a semiconductor integrated device according to claim 1 , wherein the first additional FET, the third additional FET, the sixth additional FET and the eighth additional FET each have a channel of the first conductivity type, and the second additional FET, the fourth additional FET, the fifth additional FET and the seventh additional FET each have a channel of the second conductivity type.
5. The delay circuit of a semiconductor integrated device according to claim 1 , wherein each said first FET is an n-channel MOSFET, and each said second FET is a p-channel MOSFET.
6. The delay circuit of a semiconductor integrated device according to claim 1 , wherein how many said inverters are included in the delay circuit is determined by a desired delay time provided by the delay circuit.
7. The delay circuit of a semiconductor integrated device according to claim 1 , wherein the first potential is a power source potential and the second potential is a ground potential.
8. An inverter of a semiconductor integrated device for generating a signal having an inverted level of an input signal, the inverter comprising:
a pair of first FETs that each have a channel of a first conductivity type, a drain of one of the first FETs and a source of the other being connected to each other at a first connection node, gates of both the first FETs being connected to each other at an input node, a first potential being always applied to a source of the one of the first FETs as long as the semiconductor integrated device is in operation, and a drain of the other being connected to an output node;
a pair of second FETs that each have a channel of a second conductivity type, a drain of one of the second FETs and a source of the other being connected to each other at a second connection node, gates of both the second FETs being connected to each other at the input node, a second potential being always applied to a source of the one of the second FETs as long as the semiconductor integrated device is in operation, a drain of the other being connected to the output node;
a first additional FET that applies the second potential to the first connection node when a potential at the output node becomes the second potential;
a second additional FET that always supplies the second potential to the first additional FET as long as the semiconductor integrated device is in operation;
a third additional FET whose source receives the first potential and whose drain is connected to a gate of the second additional FET;
a fourth additional FET whose source receives the second potential and whose gate and drain are both connected to a gate of the third additional FET;
a fifth additional FET that applies the first potential to the second connection node when a potential at the output node becomes the first potential;
a sixth additional FET that always supplies the first potential to the fifth additional FET as long as the semiconductor integrated device is in operation;
a seventh additional FET whose source receives the second potential and whose drain is connected to a gate of the sixth additional FET; and
an eighth additional FET whose source receives the first potential and whose gate and drain are both connected to a gate of the seventh additional FET.
9. The inverter of a semiconductor integrated device according to claim 8 , wherein the first potential is applied to the source of the one of the first FETs through a first resistor, and the second potential is applied to the source of the one of the second FETs through a second resistor.
10. The inverter according to claim 9 , wherein the first resistor has a variable resistance, and the second resistor has a variable resistance.
11. The inverter of a semiconductor integrated device according to claim 8 , wherein the first additional FET, the third additional FET, the sixth additional FET and the eighth additional FET each have a channel of the first conductivity type, and the second additional FET, the fourth additional FET, the fifth additional FET and the seventh additional FET each have a channel of the second conductivity type.
12. The inverter according to claim 8 , wherein each said first FET is an n-channel MOSFET, and each said second FET is a p-channel MOSFET.
13. The inverter according to claim 8 , wherein the first potential is a power source potential and the second potential is a ground potential.
14. A delay circuit of a semiconductor integrated device comprising an inverter of claim 8 .