WIDE BANDWIDTH DISCRETE DIGITAL RECEIVER
A receiver includes a sample and hold module, a discrete time filter module, and a wireless frequency to baseband conversion module. The sample and hold module is operable to sample and hold an inbound wireless signal at a rate corresponding to a multiple of a carrier frequency of the inbound wireless signal to produce a frequency domain sample pulse train. The discrete time filter module is operable to filter the frequency domain sample pulse train to produce a wireless frequency pulse. The wireless frequency to baseband conversion module is operable to convert the wireless frequency pulse to a baseband digital signal.
1 . A receiver comprises:
a sample and hold module operable to sample and hold an inbound wireless signal at a rate corresponding to a multiple of a carrier frequency of the inbound wireless signal to produce a frequency domain sample pulse train;
a discrete time filter module operable to filter the frequency domain sample pulse train to produce a wireless frequency pulse; and
a wireless frequency to baseband conversion module operable to convert the wireless frequency pulse to a baseband digital signal.
2 . The receiver of claim 1 further comprises:
an analog to digital conversion module operable to convert the baseband digital signal into an inbound baseband signal.
3 . The receiver of claim 2 further comprises:
a clock generation circuit operable to provide clock inputs to the sample and hold module, the discrete time filter module, and the analog to digital conversion module, the clock generation circuit including:
a clock generation module operable to generate a system clock signal;
a sample and hold clock module operable to generate, from the system clock signal, a sample and hold clock signal at the rate corresponding to the multiple of the carrier frequency of the in inbound wireless signal;
a discrete time filter clock module operable to generate a filter clock from the system clock signal; and
an analog to digital conversion (ADC) clock module operable to generate an ADC clock signal from the system clock signal.
4 . The receiver of claim 1 , wherein the wireless frequency to baseband conversion module comprises:
a second sample and hold module operable to sample and hold, at a rate corresponding to a multiple of the bandwidth of the wireless frequency pulse, the wireless frequency pulse to produce a second frequency domain sample pulse train;
a second discrete time filter module operable to filter the second frequency domain sample pulse train to produce the baseband digital signal.
5 . The receiver of claim 1 , wherein the wireless frequency to baseband conversion module comprises a down conversion module, the down conversion module operable to:
mix the wireless frequency pulse with a local oscillation to produce a mixed signal; and
filter the mixed signal to produce the baseband digital signal.
6 . The receiver of claim 1 further comprises:
a low noise amplifier (LNA) module coupled to an input of the sample and hold module, the LNA operable to amplify the inbound wireless signal.
7 . The receiver of claim 1 further comprises:
a buffer module operably coupled to an input of the sample and hold module, wherein the buffer module is operable to buffer the inbound wireless signal prior to sampling and holding by the sample and hold module.
8 . The receiver of claim 7 , wherein the buffer module comprises at least one of:
a buffer; and
an inverter.
9 . A receiver comprises:
a sample and hold module operable to sample and hold an inbound wireless signal at a rate corresponding to a multiple of a carrier frequency of the inbound wireless signal to produce a frequency domain sample pulse train;
a frequency translation bandpass filter (FTBPF) operable to bandpass filter the frequency domain sample pulse train to produce a filtered inbound wireless signal; and
a wireless frequency to baseband conversion module to convert the wireless frequency pulse to a baseband digital signal.
10 . The receiver of claim 9 further comprises:
an analog to digital conversion module operable to convert the baseband digital signal into an inbound baseband signal.
11 . The receiver of claim 10 further comprises:
a clock generation circuit operable to provide clock inputs to the sample and hold module, the FTBPF module, and the analog to digital conversion module, the clock generation circuit including:
a clock generation module operable to generate a system clock signal;
a sample and hold clock module operable to generate, from the system clock signal, a sample and hold clock signal at the rate corresponding to the multiple of the carrier frequency of the in inbound wireless signal;
an FTBPF clock module operable to generate a filter clock from the system clock signal; and
an analog to digital conversion (ADC) clock module operable to generate an ADC clock signal from the system clock signal.
12 . The receiver of claim 9 , wherein the wireless frequency to baseband conversion module comprises:
a second sample and hold module operable to sample and hold, at a rate corresponding to a multiple of the bandwidth of the wireless frequency pulse, the wireless frequency pulse to produce a second frequency domain sample pulse train;
a second discrete time filter module operable to filter the second frequency domain sample pulse train to produce the baseband digital signal.
13 . The receiver of claim 9 , wherein the wireless frequency to baseband conversion module comprises a down conversion module, the down conversion module operable to:
mix the wireless frequency pulse with a local oscillation to produce a mixed signal; and
filter the mixed signal to produce the baseband digital signal.
14 . The receiver of claim 9 further comprises:
a low noise amplifier (LNA) module coupled to an input of the sample and hold module, the LNA operable to amplify the inbound wireless signal.
15 . The receiver of claim 9 further comprises:
a buffer module operably coupled to an input of the sample and hold module, wherein the buffer module is operable to buffer the inbound wireless signal prior to sampling and holding by the sample and hold module.
16 . The receiver of claim 15 , wherein the buffer module comprises at least one of:
a buffer; and
an inverter.
17 . A receiver comprising:
a sample and hold filter operable to sample and hold an inbound wireless signal at a rate corresponding to a multiple of a carrier frequency of the inbound wireless signal to produce a frequency domain sample pulse train;
a low noise amplifier coupled to an input of the sample and hold filter;
a discrete time filter operable to filter the frequency domain sample pulse train to produce a wireless frequency pulse; and
a wireless frequency to baseband conversion module operable to convert the wireless frequency pulse to a baseband digital signal.
18 . The receiver of claim 17 , further comprising:
a clock generation circuit coupled to provide clock inputs to the sample and hold filter, and the discrete time filter.
19 . The receiver of claim 17 , wherein the wireless frequency to baseband conversion module further comprising:
a down conversion module including a mixer and a filter.
20 . The receiver of claim 17 , further comprising:
an inverting buffer coupled to an input of the sample and hold filter, and operable to buffer the inbound wireless signal prior to sampling and holding by the sample and hold module.