IP Library Granted Patent US 8,619,888
Granted Patent B2
US 8,619,888 · App. 13/241,425 · Granted Dec 31, 2013

Multiple path discrete digital receiver

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,619,888
App. No.
13/241,425
Granted
Dec 31, 2013
Kind
B2
Abstract

A receiver includes a bandpass filter module, a sample and hold module, first and second discrete time filter modules, and first and second conversion modules. The bandpass filter module is operable to filter an inbound wireless signal. The sample and hold module is operable to sample and hold the filtered inbound wireless signal to produce a frequency domain sample pulse train. The first discrete time filter module is operable to filter the frequency domain sample pulse train to produce a first filtered sample pulse. The second discrete time filter module is operable to filter the frequency domain sample pulse train to produce a second filtered sample pulse. The first conversion module is operable to convert the first filtered sample pulse into a first inbound baseband signal. The second conversion module is operable to convert the second filtered sample pulse into a second inbound baseband signal.

Claims (98)

1. A receiver comprises:

a bandpass filter module configured to filter an inbound wireless signal to produce a filtered inbound wireless signal;

a sample and hold module configured to sample and hold, at a rate corresponding to a multiple of a bandwidth of the filtered inbound wireless signal, the filtered inbound wireless signal to produce a frequency domain sample pulse train;

a first discrete time filter module configured to filter, using a first bandpass filter response, the frequency domain sample pulse train to produce a first filtered sample pulse;

a second discrete time filter module configured to filter, using a second bandpass filter response, the frequency domain sample pulse train to produce a second filtered sample pulse;

a first conversion module configured to convert the first filtered sample pulse into a first inbound baseband signal; and

a second conversion module configured to convert the second filtered sample pulse into a second inbound baseband signal.

2. The receiver of claim 1 further comprises:

a processing module configured to:

process the first and second inbound baseband signals to produce an inbound signal; and

convert the inbound signal into inbound data.

3. The receiver of claim 2 , wherein the processing module processes the first and second inbound baseband signals by at least one of:

selecting one of the first and second inbound baseband signals as the inbound signal;

combining the first and second inbound baseband signals using an averaging function to produce the inbound signal;

combining the first and second inbound baseband signals using a weighted average function to produce the inbound signal;

combining the first and second inbound baseband signals using a root mean square function to produce the inbound signal; and

combining the first and second inbound baseband signals using a mathematical function to produce the inbound signal.

4. The receiver of claim 1 , wherein:

the first discrete time filter module is configured to produce a wireless frequency sample pulse as the first filtered sample pulse;

the second discrete time filter module is configured to produce an intermediate frequency (IF) sample pulse as the second filtered sample pulse;

the first conversion module includes:

a wireless frequency to baseband conversion module configured to convert the wireless frequency sample pulse to a first baseband signal; and

a first analog to digital conversion module configured to convert the first baseband signal into the first inbound baseband signal; and

the second conversion module includes:

an IF to baseband conversion module configured to convert the IF sample pulse to a second baseband signal; and

a second analog to digital conversion module configured to convert the second baseband signal into the second inbound baseband signal.

5. The receiver of claim 1 , wherein:

the first discrete time filter module is configured to produce a wireless frequency sample pulse as the first filtered sample pulse;

the second discrete time filter module is configured to produce a baseband sample pulse as the second filtered sample pulse;

the first conversion module includes:

a wireless frequency to baseband conversion module configured to convert the wireless frequency sample pulse to a baseband signal; and

a first analog to digital conversion module configured to convert the baseband signal into the first inbound baseband signal; and

the second conversion module includes:

a second analog to digital conversion module configured to convert the baseband sample pulse into the second inbound baseband signal.

6. The receiver of claim 1 , wherein:

the first discrete time filter module is configured to produce an intermediate frequency (IF) sample pulse as the first filtered sample pulse;

the second discrete time filter module is configured to produce a baseband sample pulse as the second filtered sample pulse;

the first conversion module includes:

a wireless frequency to baseband conversion module configured to convert the IF sample pulse to a first baseband signal; and

a first analog to digital conversion module configured to convert the first baseband signal into the first inbound baseband signal; and

the second conversion module includes:

a second analog to digital conversion module configured to convert the baseband sample pulse into the second inbound baseband signal.

7. The receiver of claim 1 further comprises:

a clock generation circuit including:

a clock generation module configured to generate a system clock signal;

a sample and hold clock module configured to generate, from the system clock signal, a sample and hold clock signal for the sample and hold module at the rate corresponding to the multiple of the bandwidth of the filtered inbound wireless signal;

a first discrete time filter clock module configured to generate a first filter clock for the first discrete time filter module from the system clock signal;

a second discrete time filter clock module configured to generate a second filter clock for the second discrete time filter module from the system clock signal;

a first conversion clock module configured to generate a first conversion clock signal for the first conversion module from the system clock signal; and

a second conversion clock module configured to generate a second conversion clock signal for the second conversion module from the system clock signal.

8. A receiver comprises:

a bandpass filter module configured to filter an inbound wireless signal to produce a filtered inbound wireless signal having a bandwidth;

a sample and hold module configured to sample and hold, at a rate corresponding to a multiple of the bandwidth of the filtered inbound wireless signal, the filtered inbound wireless signal to produce a frequency domain sample pulse train;

a plurality of discrete time filter modules configured to produce a plurality of filtered sample pulses from the frequency domain sample pulse train, wherein a first discrete time filter module of the plurality of discrete time filter modules is configured to filter, using a first bandpass filter response, the frequency domain sample pulse train to produce a first filtered sample pulse of the plurality of filtered sample pulses and a second discrete time filter module of the plurality of discrete time filter modules is configured to filter, using a second bandpass filter response, the frequency domain sample pulse train to produce a second filtered sample pulse of the plurality of filtered sample pulses; and

a conversion module comprising:

a combining module configured to combine at least two of the plurality of filtered sample pulses into a combined sample pulse; a down conversion module, when the combined sample pulse is at an intermediate frequency (IF) or at a wireless frequency, configured to convert the combined sample pulse into a baseband sample pulse; and an analog to digital conversion module configured to: convert the combined sample pulse into one or more inbound baseband signals when the combined sample pulse is at baseband, and

convert the baseband sample pulse into one or more inbound baseband signals when the combined sample pulse is at the IF or the wireless frequency.

9. The receiver of claim 8 , further comprising:

a processing module configured to:

process the one or more inbound baseband signals to produce an inbound signal; and

convert the inbound signal into inbound data.

10. The receiver of claim 9 , wherein the one or more inbound baseband signals comprise at least a first and second inbound baseband signal and the processing module processes the at least first and second inbound baseband signals by at least one of:

selecting one of the first and second inbound baseband signals as the inbound signal;

combining the first and second inbound baseband signals using an averaging function to produce the inbound signal;

combining the first and second inbound baseband signals using a weighted average function to produce the inbound signal;

combining the first and second inbound baseband signals using a root mean square function to produce the inbound signal; and

combining the first and second inbound baseband signals using a mathematical function to produce the inbound signal.

11. The receiver of claim 8 , further comprises:

a clock generation circuit including:

a clock generation module configured to generate a system clock signal;

a sample and hold clock module configured to generate, from the system clock signal, a sample and hold clock signal for the sample and hold module at the rate corresponding to the multiple of the bandwidth of the filtered inbound wireless signal;

a first discrete time filter clock module configured to generate a first filter clock for the first discrete time filter module from the system clock signal;

a second discrete time filter clock module configured to generate a second filter clock for the second discrete time filter module from the system clock signal; and

a conversion clock module configured to generate at least one first conversion clock signal for the conversion module from the system clock signal.

12. A receiver comprises:

a bandpass filter module configured to filter an inbound wireless signal to produce a filtered inbound wireless signal;

a first sample and hold module configured to sample and hold, at a rate corresponding to a multiple of a bandwidth of the filtered inbound wireless signal, the filtered inbound wireless signal to produce a first frequency domain sample pulse train;

a first discrete time filter module configured to filter the first frequency domain sample pulse train to produce a first filtered sample pulse;

a first conversion module configured to convert the first filtered sample pulse into a first inbound baseband signal;

a second sample and hold module configured to sample and hold, at a rate corresponding to a multiple of a wireless frequency of the filtered inbound wireless signal, the filtered inbound wireless signal to produce a second frequency domain sample pulse train;

a second discrete time filter module configured to filter the second frequency domain sample pulse train to produce a second filtered sample pulse; and

a second conversion module configured to convert the second filtered sample pulse into a second inbound baseband signal.

13. The receiver of claim 12 , wherein:

the first discrete time filter module uses a first bandpass filter response to filter the first frequency domain sample pulse train; and

the second discrete time filter module uses a second bandpass filter response to filter the second frequency domain sample pulse train.

14. The receiver of claim 12 , wherein:

the first discrete time filter module uses a bandpass filter response to filter the first frequency domain sample pulse train; and

the second discrete time filter module uses the bandpass filter response to filter the second frequency domain sample pulse train.

15. The receiver of claim 12 further comprises:

a processing module configured to:

process the first and second inbound baseband signals to produce an inbound signal; and

convert the inbound signal into inbound data.

16. The receiver of claim 15 , wherein the processing module processes the first and second inbound baseband signals by at least one of:

selecting one of the first and second inbound baseband signals as the inbound signal;

combining the first and second inbound baseband signals using an averaging function to produce the inbound signal;

combining the first and second inbound baseband signals using a weighted average function to produce the inbound signal;

combining the first and second inbound baseband signals using a root mean square function to produce the inbound signal; and

combining the first and second inbound baseband signals using a mathematical function to produce the inbound signal.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2011
From: ROFOUGARAN, AHMADREZA (REZA); DARABI, HOOMAN
To: BROADCOM CORPORATION
Reel/Frame 026970/0261 →