Multiple input discrete digital receiver
View Patent ↗A receiver includes a sample and hold module, a discrete time filter module, and a conversion module. The sample and hold module is operable to sample and hold a first inbound wireless signal and a second inbound wireless signal to produce a frequency domain sample pulse train. The discrete time filter module is operable to filter the frequency domain sample pulse train to produce a first filtered sample pulse corresponding to the first inbound wireless signal and to produce a second filtered sample pulse corresponding to the second inbound wireless signal. The conversion module is operable to convert the first filtered sample pulse into a first inbound baseband signal and to convert the second filtered sample pulse into a second inbound baseband signal.
1. A receiver comprises:
first and second sample and hold circuitry configured to sample and hold a first inbound wireless signal to produce a first frequency domain sample pulse train and a second inbound wireless signal to produce a second frequency domain sample pulse train, wherein each of the first and second sample and hold circuitry is clocked at a rate corresponding to a multiple of a combination of frequency components of the first and second inbound wireless signals;
first and second discrete time filter circuitry configured to filter the first frequency domain sample pulse train to produce a first filtered sample pulse corresponding to the first inbound wireless signal and filter the second frequency domain sample pulse train to produce a second filtered sample pulse corresponding to the second inbound wireless signal;
first conversion circuitry configured to convert the first filtered sample pulse into a first inbound baseband signal; and
second conversion circuitry configured to convert the second filtered sample pulse into a second inbound baseband signal.
2. The receiver of claim 1 further comprises:
a first bandpass filter configured to filter a first received wireless signal to produce the first inbound wireless signal; and
a second bandpass filter configured to filter a second received wireless signal to produce the second inbound wireless signal,
wherein the first inbound wireless signal has a first bandwidth and the second inbound wireless signal has a second bandwidth, and wherein a bandwidth that spans the first and second bandwidths provides the combination of the frequency components of the first and second inbound wireless signals.
3. The receiver of claim 1 , wherein:
the first and second discrete time filter circuitry is further configured to:
filter, using a first wireless frequency bandpass filter response, the first frequency domain sample pulse train to produce the first filtered sample pulse at a first wireless frequency, and
filter, using a second wireless frequency bandpass filter response, the second frequency domain sample pulse train to produce the second filtered sample pulse at a second wireless frequency;
the first conversion circuitry includes:
a first conversion module configured to convert the first filtered sample pulse into a first down converted signal, and
a first analog to digital converter configured to convert the first down converted signal into the first inbound baseband signal; and
the second conversion circuitry includes:
a second conversion module configured to convert the second filtered sample pulse into a second down converted signal, and
a second analog to digital converter configured to convert the second down converted signal into the second inbound baseband signal.
4. The receiver of claim 1 , wherein:
the first and second discrete time filter circuitry is further configured to:
filter, using a first baseband bandpass filter response, the first frequency domain sample pulse train to produce the first filtered sample pulse at a first baseband, and
filter, using a second baseband bandpass filter response, the second frequency domain sample pulse train to produce the second filtered sample pulse at a second baseband;
the first conversion circuitry includes a first analog to digital converter configured to convert the first filtered sample pulse into the first inbound baseband signal; and
the second conversion circuitry includes a second analog to digital converter configured to convert the second filtered sample pulse into the second inbound baseband signal.
5. The receiver of claim 1 , wherein:
the first inbound wireless signal is in accordance with a first wireless communication protocol; and
the second inbound wireless signal is in accordance with a second wireless communication protocol.
6. The receiver of claim 1 further comprises:
a clock generation circuitry including:
a clock generation module configured to generate a system clock signal;
first and second sample and hold clock circuitry configured to generate, from the system clock signal, first and second sample and hold clock signals for the first and second sample and hold circuitry at the rate corresponding to the multiple of the combination of the frequency components of the first and second inbound wireless signals;
first and second discrete time filter clock circuitry configured to generate a first filter clock and a second filter clock from the system clock signal for the first and second discrete time filter circuitry; and
first and second conversion clock circuitry configured to generate a first conversion clock signal and a second conversion clock signal for the first and second conversion circuitry from the system clock signal.
7. The receiver of claim 1 , further comprises:
a third sample and hold circuit configured to sample and hold a third inbound wireless signal to produce a third frequency domain sample pulse train, wherein the third sample and hold circuit is clocked at a rate corresponding to a multiple of a combination of frequency components of the first, second, and third inbound wireless signals;
a third discrete time filter circuit configured to filter the third frequency domain sample pulse train to produce a third filtered sample pulse corresponding to the third inbound wireless signal; and
a third conversion circuit configured to convert the third filtered sample pulse into a third inbound baseband signal.
8. A receiver comprises:
a first sample and hold circuit configured to sample and hold a first inbound wireless signal to produce a first frequency domain sample pulse train;
a second sample and hold circuit configured to sample and hold a second inbound wireless signal to produce a second frequency domain sample pulse train, wherein each of the first and second sample and hold circuitry is clocked at a first rate for sampling and holding the first inbound wireless signal and a second rate for sampling and holding the second inbound wireless signal, respectively;
a first discrete time filter circuit configured to filter the first frequency domain sample pulse train to produce a first filtered sample pulse;
a second discrete time filter circuit configured to filter the second frequency domain sample pulse train to produce a second filtered sample pulse;
first conversion circuitry configured to convert the first filtered sample pulse into a first inbound baseband signal; and
second conversion circuitry configured to convert the second filtered sample pulse into a second inbound baseband signal.
9. The receiver of claim 8 , wherein:
the first rate corresponds to a multiple of a carrier frequency of the first inbound wireless signal; and
the second rate corresponds to a multiple of a carrier frequency of the second inbound wireless signal.
10. The receiver of claim 8 further comprises:
a first bandpass filter configured to bandpass filter a first received wireless signal to produce the first inbound wireless signal; and
a second bandpass filter configured to bandpass filter a second received wireless signal to produce the second inbound wireless signal,
wherein the first rate corresponds to a multiple of a bandwidth of the first inbound wireless signal and the second rate corresponds to a multiple of a bandwidth of the second inbound wireless signal.
11. The receiver of claim 8 , wherein:
the first discrete time filter circuit is further configured to filter, using a first wireless frequency bandpass filter response, the first frequency domain sample pulse train to produce the first filtered sample pulse at a first wireless frequency;
the second discrete time filter circuit is further configured to filter, using a second wireless frequency bandpass filter response, the second frequency domain sample pulse train to produce the second filtered sample pulse at a second wireless frequency;
the first conversion circuitry includes:
a first conversion module configured to convert the first filtered sample pulse into a first down converted signal, and
a first analog to digital converter configured to convert the first down converted signal into the first inbound baseband signal; and
the second conversion circuitry includes:
a second conversion module configured to convert the second filtered sample pulse into a second down converted signal, and
a second analog to digital converter configured to convert the second down converted signal into the second inbound baseband signal.
12. The receiver of claim 8 , wherein:
the first discrete time filter circuit is further configured to filter, using a first baseband bandpass filter response, the first frequency domain sample pulse train to produce the first filtered sample pulse at a first baseband;
the second discrete time filter circuit is further configured to filter, using a second baseband bandpass filter response, the second frequency domain sample pulse train to produce the second filtered sample pulse at a second baseband;
the first conversion circuitry includes a first analog to digital converter configured to convert the first filtered sample pulse into the first inbound baseband signal; and
the second conversion circuitry includes a second analog to digital converter configured to convert the second filtered sample pulse into the second inbound baseband signal.
13. The receiver of claim 8 further comprises:
clock generation circuitry including:
a clock generation module configured to generate a system clock signal;
first and second sample and hold clock circuitry configured to generate, from the system clock signal, first and second sample and hold (S&H) clock signals for the first and second sample and hold circuitry corresponding to the first rate and the second rate;
first and second discrete time filter clock circuitry configured to generate a first filter clock and a second filter clock from the system clock signal for the first and second discrete time filter circuitry; and
first and second conversion clock circuitry configured to generate first and second conversion clock signals for the first and second conversion circuitry from the system clock signal.