Low phase-noise PLL synthesizer with frequency accuracy indicator
View Patent ↗A phase-locked loop (PLL) frequency synthesizer includes a phase detector, a low pass filter coupled to the phase detector, an amplifier coupled to the low pass filter, a voltage controlled oscillator (VCO) coupled to the amplifier, a power splitter coupled to the VCO, and a switch configured to select between a first branch and a second branch through which to couple the power splitter to the phase detector. The first branch includes a frequency divider while the second branch includes a mixer. The PLL frequency synthesizer also includes a frequency accuracy indicator that compares a frequency in the first branch with a frequency generated in the second branch, and confirms that the PLL frequency synthesizer is locked to a desired frequency upon receiving a phase lock signal, if the frequency generated in the first branch is the same as the frequency generated in the second branch.
1. A phase-locked loop (PLL) frequency synthesizer comprising:
a phase detector;
a low pass filter coupled to the phase detector;
an amplifier coupled to the low pass filter;
a voltage controlled oscillator (VCO) coupled to the amplifier;
a power splitter coupled to the VCO;
a switch configured to select between a first branch and a second branch through which to couple the power splitter to the phase detector, the first branch comprising a frequency divider and the second branch comprising a mixer; and
a frequency accuracy indicator configured to compare a frequency generated in the first branch to a frequency generated in the second branch.
2. The PLL frequency synthesizer of claim 1 wherein, the frequency accuracy indicator is configured to indicate that the synthesizer is locked to a desired frequency when:
the frequency in the first branch is commensurate with the frequency generated in the second branch; and
the frequency accuracy indicator receives a phase lock signal.
3. The PLL frequency synthesizer of claim 2 wherein, the PLL frequency synthesizer is configured to generate the phase lock signal by comparing a VCO tuning voltage to a reference level.
4. The PLL frequency synthesizer of claim 2 wherein, the phase detector is configured to generate the phase lock signal.
5. The PLL frequency synthesizer of claim 1 wherein, the frequency divider has an output configured to provide the frequency generated in the first branch.
6. The PLL frequency synthesizer of claim 1 further comprising:
a reference frequency source; and
a frequency divider configured to divide an output of the reference frequency source to generate a phase comparison signal for the phase detector, to determine the frequency generated in the second branch.
7. The PLL frequency synthesizer of claim 1 further comprising:
a reference frequency source; and
a frequency multiplier configured to multiply an output of the reference frequency source to generate a local oscillator signal for the mixer, to determine the frequency generated in the second branch.
8. The PLL frequency synthesizer of claim 1 wherein, the frequency accuracy indicator comprises:
a mixer;
a low pass filter coupled to the mixer, and configured to remove sum frequency mixer products;
a high pass filter coupled to the low pass filter, and configured to determine an accuracy of the frequency accuracy indicator; and
a detector configured to rectify an output of the high pass filter.
9. The PLL frequency synthesizer of claim 8 , wherein the frequency accuracy indicator further comprises:
an inverter configured to invert a logical output of the phase detector; and,
an AND gate coupled to combine an output of the inverter and a logical phase lock signal.
10. A phase-locked loop (PLL) frequency synthesizer comprising:
a phase detector; a low pass filter; an amplifier; a voltage controlled oscillator (VCO);
an initial tuning loop comprising a frequency divider;
a mixer loop without a frequency divider; and
a frequency accuracy indicator;
wherein the PLL frequency synthesizer is configured to switch between the initial tuning loop for frequency acquisition and the mixer loop for low phase-noise performance; and
wherein the frequency accuracy indicator is configured to indicate whether the PLL frequency synthesizer is locked to a frequency determined by the divider loop when the PLL frequency synthesizer is operating with the mixer loop.