IP Library Patent Application 13242078
Patent Application
App. No. 13/242,078

SUB-MICRON CMOS VCO THAT USES DELAY-BASED CALIBRATION AND METHOD OF OPERATION

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Patent No.
US None
App. No.
13/242,078
Abstract

A system for calibrating a circuit comprising a delay to voltage converter for receiving an input signal and generating an output signal that represents a delay metric. A counter for receiving the output signal and generating a binary output as a function of the delay metric.

Claims (30)

1 . A system for calibrating a circuit comprising:

a delay to voltage converter for receiving an input signal and generating an output signal that represents a delay metric; and

a counter for receiving the output signal and generating a binary output as a function of the delay metric.

2 . The system of claim 1 further comprising a delay for generating the input signal, wherein the input signal comprises a pulse having a width proportional to the delay metric.

3 . The system of claim 1 wherein the delay metric is a function of PVT variations.

4 . The system of claim 1 further comprising:

a voltage reference; and

a comparator for receiving the voltage reference and the output signal from the delay to voltage converter, wherein the comparator is for generating the output signal for the counter when a magnitude of the output signal from the delay to voltage converter exceeds a magnitude of the reference voltage.

5 . The system of claim 1 further comprising a plurality of switches, and each of the switches is coupled to a capacitor.

6 . The system of claim 1 further comprising a plurality of switches, and each of the switches is coupled to a capacitor, wherein each digit of the binary output controls a state of one of the switches.

7 . The system of claim 1 , further comprising a plurality of capacitor banks, wherein each capacitor bank comprises a plurality of switches, and each of the switches is coupled to a capacitor.

8 . The system of claim 7 , further comprising a plurality of inverters, and each of the inverters is coupled to one or more of the capacitor banks.

9 . The system of claim 1 , further comprising a voltage source controller coupled to the counter and receiving the binary output, wherein the binary output controls a voltage level applied to a plurality of inverters by the voltage source controller.

10 . A method for calibrating a circuit comprising:

applying a reference signal to a delay;

providing an output from the delay to a delay to voltage converter, wherein the output of the delay varies as a function of a circuit parameter of the delay; and

generating a binary output as a function of an output of the delay to voltage converter.

11 . The method of claim 10 wherein generating the binary output as the function of the output of the delay to voltage converter comprises:

comparing the output of the delay to voltage converter to a reference voltage; and

terminating a counter when the output of the delay to voltage converter exceeds the reference voltage.

12 . The method of claim 11 wherein the counter generates the binary output.

13 . The method of claim 10 further comprising controlling a plurality of switches with the binary output.

14 . The method of claim 10 further comprising controlling a state of each of a plurality of switches with the binary output, wherein each digit of the binary output controls the state of one of the switches.

15 . The method of claim 10 further comprising controlling a plurality of switches with the binary output, wherein each of the switches is coupled to a capacitor.

16 . The method of claim 10 further comprising controlling a plurality of capacitor banks with the binary output, wherein each of the capacitor banks is coupled to one or more inverter.

17 . The method of claim 10 further comprising controlling a plurality of capacitor banks with the binary output, wherein each digit of the binary output controls the state of one of a plurality of switches in each of the capacitor banks.

18 . The method of claim 17 further comprising controlling a voltage level controller with the binary output, wherein the voltage level controller controls two or more voltage levels applied to a plurality of inverters as a function of the binary output.

19 . A system for calibrating a circuit comprising:

means for receiving an input signal and generating an output signal that represents a delay metric; and

means for receiving the output signal and generating a binary output as a function of the delay metric.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: LAKESTAR SEMI INC.
To: CONEXANT SYSTEMS, INC.
Reel/Frame 038803/0693 →
CHANGE OF NAME Recorded May 20, 2016
From: CONEXANT SYSTEMS, INC.
To: LAKESTAR SEMI INC.
Reel/Frame 038777/0885 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: CONEXANT SYSTEMS, INC.; CONEXANT, INC.; CONEXANT SYSTEMS WORLDWIDE, INC.; BROOKTREE BROADBAND HOLDING, INC.
Reel/Frame 038631/0452 →
SECURITY AGREEMENT Recorded Oct 7, 2011
From: CONEXANT SYSTEMS, INC.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 027035/0026 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2011
From: MOCHERLA, VAMSI
To: CONEXANT SYSTEMS, INC.
Reel/Frame 026987/0932 →