High performance divider using feed forward, clock amplification and series peaking inductors
A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.
1. A switched differential amplifier comprising:
a first differential cell driven by a differential input signal;
a first load with a first center tap couples a first leg of the first differential cell to a first power supply;
a second load with a second center tap couples a second leg of the first differential cell to the first power supply;
a plurality of switches for coupling a source of the first differential cell to a second power supply;
each of the plurality of switches receiving a different clock signal;
at least one of the different clock signals has a different phase than the remaining signals; and
the first and second center taps are coupled to a non-clocked version of the differential input signal.
2. The apparatus of claim 1 , further comprising:
a second differential cell driven by the differential input signal;
each leg of the second differential cell corresponds to an equivalent leg in the first differential cell;
a first leg of the second differential cell is coupled to the first center tap;
a second leg of the second differential cell is coupled to the second center tap;
a transistor for coupling a source of the second differential cell to the second power supply, wherein
an analog signal enables the transistor.
3. The apparatus of claim 2 , further comprising:
a current mirror coupled to the transistor that adjusts a current flow through the transistor.
4. The apparatus of claim 3 , wherein
the current flow adjusts a resonant characteristic of a RLC network.
5. The apparatus of claim 1 , wherein
each of the first and second loads is a series coupling of a resistor and a series peaking inductor.
6. The apparatus of claim 5 , further comprising:
a capacitance coupled to each leg of the first differential cell forming a RLC network.
7. The apparatus of claim 6 , whereby
the capacitance value can be electrically adjusted.
8. The apparatus of claim 7 , wherein
an impedance of the series peaking inductor matches a magnitude of the electrically adjusted impedance of the capacitor.
9. A differential amplifier comprising:
a first differential cell;
a first load with a first center tap couples a first leg of the first differential cell to a first power supply;
a second load with a second center tap couples a second leg of the first differential cell to the first power supply;
a current control for coupling the first differential cell to a second power supply;
a second differential cell;
each leg of the second differential cell corresponds to an equivalent leg in the first differential cell;
a first leg of the second differential cell is connected to the first center tap;
a second leg of the second differential cell is connected to the second center tap; and
a transistor for coupling a source of the second differential cell to the second power supply, wherein
an analog signal enables the transistor.
10. The apparatus of claim 9 , further comprising:
a plurality of switches coupled between the source of the first differential cell and the current control;
each of the plurality of switches receiving, a different signal, and
at least one of the different signals has a different phase than the remaining signals.
11. The apparatus of claim 9 , wherein
each of the first and second loads is a series coupling of a resistor and a series peaking inductor.
12. The apparatus of claim 9 , further comprising:
a capacitance coupled to each leg of the differential cell forming an RLC network.
13. The apparatus of claim 12 , whereby
the capacitance value can be electrically adjusted.
14. The apparatus of claim 13 , wherein
an impedance of the series peaking inductor matches a magnitude of the electrically adjusted impedance of the capacitor.
15. The apparatus of claim 9 , further comprising:
a current mirror coupled to the transistor that adjusts a current flow through the transistor.
16. The apparatus of claim 15 , whereby
the current flow adjusts the characteristics of the resonant RLC network.