METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER
A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting/blocking layer.
1 . An integrated circuit device comprising:
a semiconductor substrate; and
a gate stack disposed over the semiconductor substrate, wherein the gate stack includes:
a gate dielectric layer disposed over the semiconductor substrate,
a work function layer disposed over the gate dielectric layer,
a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer, and
a conductive layer disposed over the multi-function wetting/blocking layer.
2 . The integrated circuit device of claim 1 wherein the gate dielectric layer includes a high-k dielectric layer.
3 . The integrated circuit device of claim 2 wherein the gate dielectric layer includes an interfacial dielectric layer disposed between the high-k dielectric layer and the semiconductor substrate.
4 . The integrated circuit device of claim 1 wherein the titanium aluminum nitride layer has a nitrogen atomic concentration that prevents metal impurities from penetrating the gate dielectric layer.
5 . The integrated circuit device of claim 4 wherein the nitrogen atomic concentration is about 10% to about 50%.
6 . The integrated circuit device of claim 1 wherein the conductive layer is an aluminum layer.
7 . The integrated circuit device of claim 6 wherein the titanium aluminum nitride layer has a ratio of titanium, aluminum, and nitrogen that optimizes wettability between the titanium aluminum nitride layer and the aluminum layer.
8 . The integrated circuit device of claim 7 wherein the titanium aluminum nitride layer has a Ti:Al ratio of about 1:1 to about 1:3.
9 . An integrated circuit device comprising a gate stack disposed over a semiconductor substrate, wherein the gate stack includes:
a high-k dielectric layer disposed over the semiconductor substrate;
a work function layer disposed directly on the high-k dielectric layer;
a titanium aluminum nitride layer disposed directly on the work function layer; and
an aluminum layer disposed directly on the titanium aluminum nitride layer.
10 . The integrated circuit device of claim 9 wherein the titanium aluminum nitride layer has a nitrogen atomic concentration of about 10% to about 50%.
11 . The integrated circuit device of claim 9 wherein the titanium aluminum nitride layer has a Ti:Al ratio of about 1:1 to about 1:3.
12 . The integrated circuit device of claim 9 further including spacers disposed along sidewalls of the gate stack.
13 . The integrated circuit device of claim 9 wherein the gate stack interposes a source feature and a drain feature disposed in the semiconductor substrate.
14 . The integrated circuit device of claim 9 wherein the gate stack further includes an interfacial dielectric layer disposed between the high-k dielectric layer and the semiconductor substrate.
15 . A method comprising:
forming a gate structure over a semiconductor substrate, wherein the gate structure has a gate stack that includes a high-k dielectric layer disposed over the semiconductor substrate and a dummy gate disposed over the high-k dielectric layer;
removing the dummy gate from the gate structure, thereby forming an opening; and
forming a work function layer over the high-k dielectric layer, a multi-function wetting/blocking layer over the work function layer, and a conductive layer over the multi-function wetting/blocking layer, wherein the work function layer, the multi-function wetting/blocking layer, and the conductive layer fill the opening, and further wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer.
16 . The method of claim 15 wherein the forming the multi-function wetting/blocking layer over the work function layer includes performing a physical vapor deposition process.
17 . The method of claim 16 wherein the performing the physical vapor deposition process includes tuning the physical vapor deposition process such that the titanium aluminum nitride layer has a nitrogen atomic concentration of about 10% to about 50%.
18 . The method of claim 16 wherein the performing the physical vapor deposition process includes tuning the physical vapor deposition process such that the titanium aluminum nitride layer has a Ti:Al ratio of about 1:1 to about 1:3.
19 . The method of claim 16 wherein the performing the physical vapor deposition process includes performing the physical vapor deposition process at a chamber pressure of about 20 mTorr to about 40 mTorr.
20 . The method of claim 15 further including forming a source feature and a drain feature in the semiconductor substrate, wherein the gate structure interposes the source feature and the drain feature.