IP Library Granted Patent US 8,532,113
Granted Patent B2
US 8,532,113 · App. 13/245,128 · Granted Sep 10, 2013

Algorithm for managing data loss in software demodulators

Inventors: Bernard Arambepola (Middlesex, GB); Tony Cole (Swindon, GB); Parveen Shukla (Nottingham, GB); Thushara Hewavithana (Borehamwood, GB); Sahan Gamage (Cambridge, GB)
Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,532,113
App. No.
13/245,128
Granted
Sep 10, 2013
Kind
B2
Abstract

Embodiments of methods for receiving and processing multi-band signals in wideband and narrowband environments are described herein. Other embodiments may be described and claimed.

Claims (67)

1. A mobile device comprising:

a processor operatively associated with a buffer;

a communications interface operatively associated with the processor;

the communications interface being configured to:

receive data packets; and

transfer remaining blocks over a communication channel of the computing system;

the processor being configured to:

establish a unique header pattern to indicate a discontiguous stream of data packets;

add a synchronization byte to the header;

partition the data packets into a plurality of blocks;

add a header with a continuity counter to each block of the plurality of blocks;

erase one or more blocks of the plurality of blocks to form the remaining blocks;

process the remaining blocks through a shift register;

determine that the remaining blocks represent a discontiguous data stream, based on the unique header pattern;

generate pseudo noise blocks; and

replace the one or more erased blocks in the plurality of blocks with the pseudo noise blocks to provide a stream of contiguous data for demodulation; and

the buffer being configured to store the plurality of blocks.

2. The mobile device as recited in claim 1 , wherein the received data packets include a stream of multimedia data.

3. The mobile device as recited in claim 1 , wherein the received data packets include wideband data and narrowband data.

4. The mobile device as recited in claim 1 , wherein the processor is further configured to decimate the data packets.

5. A computing system comprising:

a processor operatively associated with a buffer;

a communications interface operatively associated with the processor;

the processor being configured to:

add a synchronization byte to a header;

partition received data packets into a plurality of blocks;

designate one or more blocks of the plurality of blocks as remaining blocks;

process the remaining blocks through a memory for later transmission;

determine that the remaining blocks represent a discontiguous data stream;

generate filler blocks; and

replace the one or more blocks in the plurality of blocks but not part of the remaining blocks with the filler blocks to provide a stream of contiguous data;

the communications interface being configured to:

receive the data packets; and

transfer the remaining blocks over a communication channel of the computing system; and

the buffer being configured to store the plurality of blocks.

6. The computing system as recited in claim 5 , wherein the communications interface is further configured to transfer the replacement blocks over the communication channel of the computing system.

7. The computing system as recited in claim 5 , wherein the processor is further configured to generate pseudo noise for the filler blocks.

8. The computing system as recited in claim 5 , wherein the processor is further configured to establish a unique header pattern to indicate a discontiguous stream of data packets.

9. The computing system as recited in claim 5 , wherein the processor is further configured to add a header to each block of the plurality of blocks, wherein this header includes an indication that the associated block is part of a continuity with multiple blocks of the plurality of blocks.

10. The computing system as recited in claim 5 , wherein the processor is further configured to erase one or more blocks of the plurality of blocks, thereby designating the blocks that remain as the remaining blocks.

11. The computing system as recited in claim 5 , wherein the processor is further configured to process the remaining blocks through a shift register.

12. The computing system as recited in claim 5 , wherein the processor is further configured to use a unique header pattern to determine that the remaining blocks represent a discontiguous data stream.

13. The computing system as recited in claim 5 , wherein the processor is further configured to:

establish a unique header pattern to indicate a discontiguous stream of data packets;

add a header with a continuity counter to each block of the plurality of blocks;

erase one or more blocks of the plurality of blocks to form the remaining blocks;

process the remaining blocks through a shift register; and

use the unique header pattern to determine that the remaining blocks represent a discontiguous data stream.

14. The computing system as recited in claim 5 , wherein the received data packets include a stream of multimedia data.

15. The computing system as recited in claim 5 , wherein the received data packets include wideband data and narrowband data.

16. The computing system as recited in claim 5 , wherein the processor is further configured to decimate the data packets.

17. A computing system comprising:

a processor with a operatively associated buffer;

a communications interface operatively associated with the processor;

the communications interface being configured to:

receive data packets; and

transfer remaining blocks over a communication channel of the computing system;

the processor being configured to:

partition the data packets into a plurality of blocks;

add a header to each block of the plurality of blocks, wherein this header includes an indication that the associated block is part of a continuity with multiple blocks of the plurality of blocks;

designate one or more blocks of the plurality of blocks as remaining blocks;

generate filler blocks; and

replace the one or more blocks in the plurality of blocks but not part of the remaining blocks with the filler blocks to provide a stream of contiguous data; and

the buffer being configured to store the plurality of blocks.

18. The computing system as recited in claim 17 , wherein the processor is further configured to generate pseudo noise for the filler blocks.

19. The computing system as recited in claim 17 , wherein the processor is further configured to decimate the data packets.

20. The computing system as recited in claim 17 , wherein the received data packets include a stream of multimedia data.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2018
From: SKY ROYAL TRADING LIMITED
To: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD
Reel/Frame 044750/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2018
From: INTEL CORPORATION
To: SKY ROYAL TRADING LIMITED
Reel/Frame 045171/0323 →
Continuity (2)
Continuation 12316876 · Dec 16, 2008
Related Publication 20120014372A1 · Jan 19, 2012